a030ce4477
This patch allows drm to populate an agpgart structure with pages of its own. It's needed for the new drm memory manager which dynamically flips pages in and out of AGP. The patch modifies the generic functions as well as the intel agp driver. The intel drm driver is currently the only one supporting the new memory manager. Other agp drivers may need some minor fixing up once they have a corresponding memory manager enabled drm driver. AGP memory types >= AGP_USER_TYPES are not populated by the agpgart driver, but the drm is expected to do that, as well as taking care of cache- and tlb flushing when needed. It's not possible to request these types from user space using agpgart ioctls. The Intel driver also gets a new memory type for pages that can be bound cached to the intel GTT. Signed-off-by: Thomas Hellstrom <thomas@tungstengraphics.com> Signed-off-by: Dave Jones <davej@redhat.com>
805 lines
20 KiB
C
805 lines
20 KiB
C
/*
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* Copyright 2001-2003 SuSE Labs.
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* Distributed under the GNU public license, v2.
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*
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* This is a GART driver for the AMD Opteron/Athlon64 on-CPU northbridge.
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* It also includes support for the AMD 8151 AGP bridge,
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* although it doesn't actually do much, as all the real
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* work is done in the northbridge(s).
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*/
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/agp_backend.h>
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#include <linux/mmzone.h>
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#include <asm/page.h> /* PAGE_SIZE */
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#include <asm/k8.h>
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#include "agp.h"
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/* PTE bits. */
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#define GPTE_VALID 1
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#define GPTE_COHERENT 2
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/* Aperture control register bits. */
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#define GARTEN (1<<0)
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#define DISGARTCPU (1<<4)
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#define DISGARTIO (1<<5)
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/* GART cache control register bits. */
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#define INVGART (1<<0)
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#define GARTPTEERR (1<<1)
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/* K8 On-cpu GART registers */
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#define AMD64_GARTAPERTURECTL 0x90
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#define AMD64_GARTAPERTUREBASE 0x94
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#define AMD64_GARTTABLEBASE 0x98
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#define AMD64_GARTCACHECTL 0x9c
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#define AMD64_GARTEN (1<<0)
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/* NVIDIA K8 registers */
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#define NVIDIA_X86_64_0_APBASE 0x10
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#define NVIDIA_X86_64_1_APBASE1 0x50
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#define NVIDIA_X86_64_1_APLIMIT1 0x54
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#define NVIDIA_X86_64_1_APSIZE 0xa8
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#define NVIDIA_X86_64_1_APBASE2 0xd8
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#define NVIDIA_X86_64_1_APLIMIT2 0xdc
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/* ULi K8 registers */
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#define ULI_X86_64_BASE_ADDR 0x10
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#define ULI_X86_64_HTT_FEA_REG 0x50
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#define ULI_X86_64_ENU_SCR_REG 0x54
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static struct resource *aperture_resource;
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static int __initdata agp_try_unsupported = 1;
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static void amd64_tlbflush(struct agp_memory *temp)
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{
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k8_flush_garts();
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}
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static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
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{
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int i, j, num_entries;
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long long tmp;
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int mask_type;
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struct agp_bridge_data *bridge = mem->bridge;
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u32 pte;
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num_entries = agp_num_entries();
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if (type != mem->type)
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return -EINVAL;
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mask_type = bridge->driver->agp_type_to_mask_type(bridge, type);
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if (mask_type != 0)
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return -EINVAL;
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/* Make sure we can fit the range in the gatt table. */
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/* FIXME: could wrap */
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if (((unsigned long)pg_start + mem->page_count) > num_entries)
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return -EINVAL;
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j = pg_start;
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/* gatt table should be empty. */
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while (j < (pg_start + mem->page_count)) {
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if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j)))
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return -EBUSY;
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j++;
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}
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if (mem->is_flushed == FALSE) {
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global_cache_flush();
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mem->is_flushed = TRUE;
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}
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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tmp = agp_bridge->driver->mask_memory(agp_bridge,
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mem->memory[i], mask_type);
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BUG_ON(tmp & 0xffffff0000000ffcULL);
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pte = (tmp & 0x000000ff00000000ULL) >> 28;
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pte |=(tmp & 0x00000000fffff000ULL);
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pte |= GPTE_VALID | GPTE_COHERENT;
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writel(pte, agp_bridge->gatt_table+j);
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readl(agp_bridge->gatt_table+j); /* PCI Posting. */
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}
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amd64_tlbflush(mem);
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return 0;
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}
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/*
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* This hack alters the order element according
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* to the size of a long. It sucks. I totally disown this, even
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* though it does appear to work for the most part.
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*/
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static struct aper_size_info_32 amd64_aperture_sizes[7] =
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{
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{32, 8192, 3+(sizeof(long)/8), 0 },
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{64, 16384, 4+(sizeof(long)/8), 1<<1 },
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{128, 32768, 5+(sizeof(long)/8), 1<<2 },
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{256, 65536, 6+(sizeof(long)/8), 1<<1 | 1<<2 },
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{512, 131072, 7+(sizeof(long)/8), 1<<3 },
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{1024, 262144, 8+(sizeof(long)/8), 1<<1 | 1<<3},
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{2048, 524288, 9+(sizeof(long)/8), 1<<2 | 1<<3}
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};
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/*
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* Get the current Aperture size from the x86-64.
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* Note, that there may be multiple x86-64's, but we just return
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* the value from the first one we find. The set_size functions
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* keep the rest coherent anyway. Or at least should do.
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*/
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static int amd64_fetch_size(void)
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{
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struct pci_dev *dev;
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int i;
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u32 temp;
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struct aper_size_info_32 *values;
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dev = k8_northbridges[0];
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if (dev==NULL)
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return 0;
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pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &temp);
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temp = (temp & 0xe);
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values = A_SIZE_32(amd64_aperture_sizes);
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for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
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if (temp == values[i].size_value) {
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agp_bridge->previous_size =
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agp_bridge->current_size = (void *) (values + i);
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agp_bridge->aperture_size_idx = i;
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return values[i].size;
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}
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}
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return 0;
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}
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/*
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* In a multiprocessor x86-64 system, this function gets
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* called once for each CPU.
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*/
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static u64 amd64_configure (struct pci_dev *hammer, u64 gatt_table)
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{
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u64 aperturebase;
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u32 tmp;
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u64 addr, aper_base;
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/* Address to map to */
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pci_read_config_dword (hammer, AMD64_GARTAPERTUREBASE, &tmp);
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aperturebase = tmp << 25;
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aper_base = (aperturebase & PCI_BASE_ADDRESS_MEM_MASK);
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/* address of the mappings table */
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addr = (u64) gatt_table;
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addr >>= 12;
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tmp = (u32) addr<<4;
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tmp &= ~0xf;
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pci_write_config_dword (hammer, AMD64_GARTTABLEBASE, tmp);
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/* Enable GART translation for this hammer. */
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pci_read_config_dword(hammer, AMD64_GARTAPERTURECTL, &tmp);
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tmp |= GARTEN;
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tmp &= ~(DISGARTCPU | DISGARTIO);
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pci_write_config_dword(hammer, AMD64_GARTAPERTURECTL, tmp);
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return aper_base;
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}
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static struct aper_size_info_32 amd_8151_sizes[7] =
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{
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{2048, 524288, 9, 0x00000000 }, /* 0 0 0 0 0 0 */
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{1024, 262144, 8, 0x00000400 }, /* 1 0 0 0 0 0 */
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{512, 131072, 7, 0x00000600 }, /* 1 1 0 0 0 0 */
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{256, 65536, 6, 0x00000700 }, /* 1 1 1 0 0 0 */
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{128, 32768, 5, 0x00000720 }, /* 1 1 1 1 0 0 */
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{64, 16384, 4, 0x00000730 }, /* 1 1 1 1 1 0 */
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{32, 8192, 3, 0x00000738 } /* 1 1 1 1 1 1 */
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};
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static int amd_8151_configure(void)
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{
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unsigned long gatt_bus = virt_to_gart(agp_bridge->gatt_table_real);
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int i;
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/* Configure AGP regs in each x86-64 host bridge. */
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for (i = 0; i < num_k8_northbridges; i++) {
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agp_bridge->gart_bus_addr =
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amd64_configure(k8_northbridges[i], gatt_bus);
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}
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k8_flush_garts();
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return 0;
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}
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static void amd64_cleanup(void)
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{
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u32 tmp;
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int i;
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for (i = 0; i < num_k8_northbridges; i++) {
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struct pci_dev *dev = k8_northbridges[i];
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/* disable gart translation */
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pci_read_config_dword (dev, AMD64_GARTAPERTURECTL, &tmp);
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tmp &= ~AMD64_GARTEN;
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pci_write_config_dword (dev, AMD64_GARTAPERTURECTL, tmp);
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}
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}
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static struct agp_bridge_driver amd_8151_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = amd_8151_sizes,
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.size_type = U32_APER_SIZE,
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.num_aperture_sizes = 7,
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.configure = amd_8151_configure,
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.fetch_size = amd64_fetch_size,
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.cleanup = amd64_cleanup,
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.tlb_flush = amd64_tlbflush,
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.mask_memory = agp_generic_mask_memory,
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.masks = NULL,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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.create_gatt_table = agp_generic_create_gatt_table,
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.free_gatt_table = agp_generic_free_gatt_table,
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.insert_memory = amd64_insert_memory,
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.remove_memory = agp_generic_remove_memory,
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.alloc_by_type = agp_generic_alloc_by_type,
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.free_by_type = agp_generic_free_by_type,
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.agp_alloc_page = agp_generic_alloc_page,
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.agp_destroy_page = agp_generic_destroy_page,
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.agp_type_to_mask_type = agp_generic_type_to_mask_type,
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};
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/* Some basic sanity checks for the aperture. */
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static int __devinit aperture_valid(u64 aper, u32 size)
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{
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u32 pfn, c;
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if (aper == 0) {
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printk(KERN_ERR PFX "No aperture\n");
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return 0;
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}
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if (size < 32*1024*1024) {
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printk(KERN_ERR PFX "Aperture too small (%d MB)\n", size>>20);
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return 0;
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}
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if (aper + size > 0xffffffff) {
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printk(KERN_ERR PFX "Aperture out of bounds\n");
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return 0;
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}
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pfn = aper >> PAGE_SHIFT;
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for (c = 0; c < size/PAGE_SIZE; c++) {
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if (!pfn_valid(pfn + c))
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break;
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if (!PageReserved(pfn_to_page(pfn + c))) {
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printk(KERN_ERR PFX "Aperture pointing to RAM\n");
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return 0;
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}
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}
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/* Request the Aperture. This catches cases when someone else
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already put a mapping in there - happens with some very broken BIOS
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Maybe better to use pci_assign_resource/pci_enable_device instead
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trusting the bridges? */
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if (!aperture_resource &&
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!(aperture_resource = request_mem_region(aper, size, "aperture"))) {
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printk(KERN_ERR PFX "Aperture conflicts with PCI mapping.\n");
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return 0;
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}
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return 1;
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}
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/*
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* W*s centric BIOS sometimes only set up the aperture in the AGP
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* bridge, not the northbridge. On AMD64 this is handled early
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* in aperture.c, but when IOMMU is not enabled or we run
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* on a 32bit kernel this needs to be redone.
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* Unfortunately it is impossible to fix the aperture here because it's too late
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* to allocate that much memory. But at least error out cleanly instead of
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* crashing.
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*/
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static __devinit int fix_northbridge(struct pci_dev *nb, struct pci_dev *agp,
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u16 cap)
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{
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u32 aper_low, aper_hi;
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u64 aper, nb_aper;
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int order = 0;
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u32 nb_order, nb_base;
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u16 apsize;
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pci_read_config_dword(nb, 0x90, &nb_order);
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nb_order = (nb_order >> 1) & 7;
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pci_read_config_dword(nb, 0x94, &nb_base);
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nb_aper = nb_base << 25;
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if (aperture_valid(nb_aper, (32*1024*1024)<<nb_order)) {
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return 0;
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}
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/* Northbridge seems to contain crap. Try the AGP bridge. */
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pci_read_config_word(agp, cap+0x14, &apsize);
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if (apsize == 0xffff)
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return -1;
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apsize &= 0xfff;
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/* Some BIOS use weird encodings not in the AGPv3 table. */
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if (apsize & 0xff)
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apsize |= 0xf00;
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order = 7 - hweight16(apsize);
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pci_read_config_dword(agp, 0x10, &aper_low);
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pci_read_config_dword(agp, 0x14, &aper_hi);
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aper = (aper_low & ~((1<<22)-1)) | ((u64)aper_hi << 32);
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printk(KERN_INFO PFX "Aperture from AGP @ %Lx size %u MB\n", aper, 32 << order);
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if (order < 0 || !aperture_valid(aper, (32*1024*1024)<<order))
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return -1;
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pci_write_config_dword(nb, 0x90, order << 1);
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pci_write_config_dword(nb, 0x94, aper >> 25);
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return 0;
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}
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static __devinit int cache_nbs (struct pci_dev *pdev, u32 cap_ptr)
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{
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int i;
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if (cache_k8_northbridges() < 0)
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return -ENODEV;
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i = 0;
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for (i = 0; i < num_k8_northbridges; i++) {
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struct pci_dev *dev = k8_northbridges[i];
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if (fix_northbridge(dev, pdev, cap_ptr) < 0) {
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printk(KERN_ERR PFX "No usable aperture found.\n");
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#ifdef __x86_64__
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/* should port this to i386 */
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printk(KERN_ERR PFX "Consider rebooting with iommu=memaper=2 to get a good aperture.\n");
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#endif
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return -1;
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}
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}
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return 0;
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}
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/* Handle AMD 8151 quirks */
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static void __devinit amd8151_init(struct pci_dev *pdev, struct agp_bridge_data *bridge)
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{
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char *revstring;
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u8 rev_id;
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pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
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switch (rev_id) {
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case 0x01: revstring="A0"; break;
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case 0x02: revstring="A1"; break;
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case 0x11: revstring="B0"; break;
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case 0x12: revstring="B1"; break;
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case 0x13: revstring="B2"; break;
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case 0x14: revstring="B3"; break;
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default: revstring="??"; break;
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}
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printk (KERN_INFO PFX "Detected AMD 8151 AGP Bridge rev %s\n", revstring);
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/*
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* Work around errata.
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* Chips before B2 stepping incorrectly reporting v3.5
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*/
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if (rev_id < 0x13) {
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printk (KERN_INFO PFX "Correcting AGP revision (reports 3.5, is really 3.0)\n");
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bridge->major_version = 3;
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bridge->minor_version = 0;
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}
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}
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static const struct aper_size_info_32 uli_sizes[7] =
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{
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{256, 65536, 6, 10},
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{128, 32768, 5, 9},
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{64, 16384, 4, 8},
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{32, 8192, 3, 7},
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{16, 4096, 2, 6},
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{8, 2048, 1, 4},
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{4, 1024, 0, 3}
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};
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static int __devinit uli_agp_init(struct pci_dev *pdev)
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{
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u32 httfea,baseaddr,enuscr;
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struct pci_dev *dev1;
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int i;
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unsigned size = amd64_fetch_size();
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printk(KERN_INFO "Setting up ULi AGP.\n");
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dev1 = pci_get_slot (pdev->bus,PCI_DEVFN(0,0));
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if (dev1 == NULL) {
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printk(KERN_INFO PFX "Detected a ULi chipset, "
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"but could not fine the secondary device.\n");
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return -ENODEV;
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}
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for (i = 0; i < ARRAY_SIZE(uli_sizes); i++)
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if (uli_sizes[i].size == size)
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break;
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if (i == ARRAY_SIZE(uli_sizes)) {
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printk(KERN_INFO PFX "No ULi size found for %d\n", size);
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return -ENODEV;
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}
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/* shadow x86-64 registers into ULi registers */
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pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &httfea);
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/* if x86-64 aperture base is beyond 4G, exit here */
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if ((httfea & 0x7fff) >> (32 - 25))
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return -ENODEV;
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httfea = (httfea& 0x7fff) << 25;
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pci_read_config_dword(pdev, ULI_X86_64_BASE_ADDR, &baseaddr);
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baseaddr&= ~PCI_BASE_ADDRESS_MEM_MASK;
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baseaddr|= httfea;
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pci_write_config_dword(pdev, ULI_X86_64_BASE_ADDR, baseaddr);
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enuscr= httfea+ (size * 1024 * 1024) - 1;
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pci_write_config_dword(dev1, ULI_X86_64_HTT_FEA_REG, httfea);
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pci_write_config_dword(dev1, ULI_X86_64_ENU_SCR_REG, enuscr);
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pci_dev_put(dev1);
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return 0;
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}
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static const struct aper_size_info_32 nforce3_sizes[5] =
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{
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{512, 131072, 7, 0x00000000 },
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|
{256, 65536, 6, 0x00000008 },
|
|
{128, 32768, 5, 0x0000000C },
|
|
{64, 16384, 4, 0x0000000E },
|
|
{32, 8192, 3, 0x0000000F }
|
|
};
|
|
|
|
/* Handle shadow device of the Nvidia NForce3 */
|
|
/* CHECK-ME original 2.4 version set up some IORRs. Check if that is needed. */
|
|
static int nforce3_agp_init(struct pci_dev *pdev)
|
|
{
|
|
u32 tmp, apbase, apbar, aplimit;
|
|
struct pci_dev *dev1;
|
|
int i;
|
|
unsigned size = amd64_fetch_size();
|
|
|
|
printk(KERN_INFO PFX "Setting up Nforce3 AGP.\n");
|
|
|
|
dev1 = pci_get_slot(pdev->bus, PCI_DEVFN(11, 0));
|
|
if (dev1 == NULL) {
|
|
printk(KERN_INFO PFX "agpgart: Detected an NVIDIA "
|
|
"nForce3 chipset, but could not find "
|
|
"the secondary device.\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(nforce3_sizes); i++)
|
|
if (nforce3_sizes[i].size == size)
|
|
break;
|
|
|
|
if (i == ARRAY_SIZE(nforce3_sizes)) {
|
|
printk(KERN_INFO PFX "No NForce3 size found for %d\n", size);
|
|
return -ENODEV;
|
|
}
|
|
|
|
pci_read_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, &tmp);
|
|
tmp &= ~(0xf);
|
|
tmp |= nforce3_sizes[i].size_value;
|
|
pci_write_config_dword(dev1, NVIDIA_X86_64_1_APSIZE, tmp);
|
|
|
|
/* shadow x86-64 registers into NVIDIA registers */
|
|
pci_read_config_dword (k8_northbridges[0], AMD64_GARTAPERTUREBASE, &apbase);
|
|
|
|
/* if x86-64 aperture base is beyond 4G, exit here */
|
|
if ( (apbase & 0x7fff) >> (32 - 25) ) {
|
|
printk(KERN_INFO PFX "aperture base > 4G\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
apbase = (apbase & 0x7fff) << 25;
|
|
|
|
pci_read_config_dword(pdev, NVIDIA_X86_64_0_APBASE, &apbar);
|
|
apbar &= ~PCI_BASE_ADDRESS_MEM_MASK;
|
|
apbar |= apbase;
|
|
pci_write_config_dword(pdev, NVIDIA_X86_64_0_APBASE, apbar);
|
|
|
|
aplimit = apbase + (size * 1024 * 1024) - 1;
|
|
pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE1, apbase);
|
|
pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT1, aplimit);
|
|
pci_write_config_dword(dev1, NVIDIA_X86_64_1_APBASE2, apbase);
|
|
pci_write_config_dword(dev1, NVIDIA_X86_64_1_APLIMIT2, aplimit);
|
|
|
|
pci_dev_put(dev1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __devinit agp_amd64_probe(struct pci_dev *pdev,
|
|
const struct pci_device_id *ent)
|
|
{
|
|
struct agp_bridge_data *bridge;
|
|
u8 cap_ptr;
|
|
|
|
cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
|
|
if (!cap_ptr)
|
|
return -ENODEV;
|
|
|
|
/* Could check for AGPv3 here */
|
|
|
|
bridge = agp_alloc_bridge();
|
|
if (!bridge)
|
|
return -ENOMEM;
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_AMD &&
|
|
pdev->device == PCI_DEVICE_ID_AMD_8151_0) {
|
|
amd8151_init(pdev, bridge);
|
|
} else {
|
|
printk(KERN_INFO PFX "Detected AGP bridge %x\n", pdev->devfn);
|
|
}
|
|
|
|
bridge->driver = &amd_8151_driver;
|
|
bridge->dev = pdev;
|
|
bridge->capndx = cap_ptr;
|
|
|
|
/* Fill in the mode register */
|
|
pci_read_config_dword(pdev, bridge->capndx+PCI_AGP_STATUS, &bridge->mode);
|
|
|
|
if (cache_nbs(pdev, cap_ptr) == -1) {
|
|
agp_put_bridge(bridge);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_NVIDIA) {
|
|
int ret = nforce3_agp_init(pdev);
|
|
if (ret) {
|
|
agp_put_bridge(bridge);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_AL) {
|
|
int ret = uli_agp_init(pdev);
|
|
if (ret) {
|
|
agp_put_bridge(bridge);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
pci_set_drvdata(pdev, bridge);
|
|
return agp_add_bridge(bridge);
|
|
}
|
|
|
|
static void __devexit agp_amd64_remove(struct pci_dev *pdev)
|
|
{
|
|
struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
|
|
|
|
release_mem_region(virt_to_gart(bridge->gatt_table_real),
|
|
amd64_aperture_sizes[bridge->aperture_size_idx].size);
|
|
agp_remove_bridge(bridge);
|
|
agp_put_bridge(bridge);
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int agp_amd64_suspend(struct pci_dev *pdev, pm_message_t state)
|
|
{
|
|
pci_save_state(pdev);
|
|
pci_set_power_state(pdev, pci_choose_state(pdev, state));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int agp_amd64_resume(struct pci_dev *pdev)
|
|
{
|
|
pci_set_power_state(pdev, PCI_D0);
|
|
pci_restore_state(pdev);
|
|
|
|
if (pdev->vendor == PCI_VENDOR_ID_NVIDIA)
|
|
nforce3_agp_init(pdev);
|
|
|
|
return amd_8151_configure();
|
|
}
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
static struct pci_device_id agp_amd64_pci_table[] = {
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_AMD,
|
|
.device = PCI_DEVICE_ID_AMD_8151_0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* ULi M1689 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_AL,
|
|
.device = PCI_DEVICE_ID_AL_M1689,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* VIA K8T800Pro */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_VIA,
|
|
.device = PCI_DEVICE_ID_VIA_K8T800PRO_0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* VIA K8T800 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_VIA,
|
|
.device = PCI_DEVICE_ID_VIA_8385_0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* VIA K8M800 / K8N800 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_VIA,
|
|
.device = PCI_DEVICE_ID_VIA_8380_0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* VIA K8M890 / K8N890 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_VIA,
|
|
.device = PCI_DEVICE_ID_VIA_VT3336,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* VIA K8T890 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_VIA,
|
|
.device = PCI_DEVICE_ID_VIA_3238_0,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* VIA K8T800/K8M800/K8N800 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_VIA,
|
|
.device = PCI_DEVICE_ID_VIA_838X_1,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* NForce3 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_NVIDIA,
|
|
.device = PCI_DEVICE_ID_NVIDIA_NFORCE3,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_NVIDIA,
|
|
.device = PCI_DEVICE_ID_NVIDIA_NFORCE3S,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* SIS 755 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_SI,
|
|
.device = PCI_DEVICE_ID_SI_755,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* SIS 760 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_SI,
|
|
.device = PCI_DEVICE_ID_SI_760,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
/* ALI/ULI M1695 */
|
|
{
|
|
.class = (PCI_CLASS_BRIDGE_HOST << 8),
|
|
.class_mask = ~0,
|
|
.vendor = PCI_VENDOR_ID_AL,
|
|
.device = 0x1695,
|
|
.subvendor = PCI_ANY_ID,
|
|
.subdevice = PCI_ANY_ID,
|
|
},
|
|
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(pci, agp_amd64_pci_table);
|
|
|
|
static struct pci_driver agp_amd64_pci_driver = {
|
|
.name = "agpgart-amd64",
|
|
.id_table = agp_amd64_pci_table,
|
|
.probe = agp_amd64_probe,
|
|
.remove = agp_amd64_remove,
|
|
#ifdef CONFIG_PM
|
|
.suspend = agp_amd64_suspend,
|
|
.resume = agp_amd64_resume,
|
|
#endif
|
|
};
|
|
|
|
|
|
/* Not static due to IOMMU code calling it early. */
|
|
int __init agp_amd64_init(void)
|
|
{
|
|
int err = 0;
|
|
|
|
if (agp_off)
|
|
return -EINVAL;
|
|
if (pci_register_driver(&agp_amd64_pci_driver) < 0) {
|
|
struct pci_dev *dev;
|
|
if (!agp_try_unsupported && !agp_try_unsupported_boot) {
|
|
printk(KERN_INFO PFX "No supported AGP bridge found.\n");
|
|
#ifdef MODULE
|
|
printk(KERN_INFO PFX "You can try agp_try_unsupported=1\n");
|
|
#else
|
|
printk(KERN_INFO PFX "You can boot with agp=try_unsupported\n");
|
|
#endif
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* First check that we have at least one AMD64 NB */
|
|
if (!pci_dev_present(k8_nb_ids))
|
|
return -ENODEV;
|
|
|
|
/* Look for any AGP bridge */
|
|
dev = NULL;
|
|
err = -ENODEV;
|
|
for_each_pci_dev(dev) {
|
|
if (!pci_find_capability(dev, PCI_CAP_ID_AGP))
|
|
continue;
|
|
/* Only one bridge supported right now */
|
|
if (agp_amd64_probe(dev, NULL) == 0) {
|
|
err = 0;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return err;
|
|
}
|
|
|
|
static void __exit agp_amd64_cleanup(void)
|
|
{
|
|
if (aperture_resource)
|
|
release_resource(aperture_resource);
|
|
pci_unregister_driver(&agp_amd64_pci_driver);
|
|
}
|
|
|
|
/* On AMD64 the PCI driver needs to initialize this driver early
|
|
for the IOMMU, so it has to be called via a backdoor. */
|
|
#ifndef CONFIG_IOMMU
|
|
module_init(agp_amd64_init);
|
|
module_exit(agp_amd64_cleanup);
|
|
#endif
|
|
|
|
MODULE_AUTHOR("Dave Jones <davej@codemonkey.org.uk>, Andi Kleen");
|
|
module_param(agp_try_unsupported, bool, 0);
|
|
MODULE_LICENSE("GPL");
|