5bd75403be
* remotes/origin/tmp-f686d9f:
ANDROID: update abi_gki_aarch64.xml for 5.2-rc6
Linux 5.2-rc6
Revert "iommu/vt-d: Fix lock inversion between iommu->lock and device_domain_lock"
Bluetooth: Fix regression with minimum encryption key size alignment
tcp: refine memory limit test in tcp_fragment()
x86/vdso: Prevent segfaults due to hoisted vclock reads
SUNRPC: Fix a credential refcount leak
Revert "SUNRPC: Declare RPC timers as TIMER_DEFERRABLE"
net :sunrpc :clnt :Fix xps refcount imbalance on the error path
NFS4: Only set creation opendata if O_CREAT
ANDROID: gki_defconfig: workaround to enable configs
ANDROID: gki_defconfig: more configs for partners
ARM: 8867/1: vdso: pass --be8 to linker if necessary
KVM: nVMX: reorganize initial steps of vmx_set_nested_state
KVM: PPC: Book3S HV: Invalidate ERAT when flushing guest TLB entries
habanalabs: use u64_to_user_ptr() for reading user pointers
nfsd: replace Jeff by Chuck as nfsd co-maintainer
inet: clear num_timeout reqsk_alloc()
PCI/P2PDMA: Ignore root complex whitelist when an IOMMU is present
net: mvpp2: debugfs: Add pmap to fs dump
ipv6: Default fib6_type to RTN_UNICAST when not set
net: hns3: Fix inconsistent indenting
net/af_iucv: always register net_device notifier
net/af_iucv: build proper skbs for HiperTransport
net/af_iucv: remove GFP_DMA restriction for HiperTransport
doc: fix documentation about UIO_MEM_LOGICAL using
MAINTAINERS / Documentation: Thorsten Scherer is the successor of Gavin Schenk
docs: fb: Add TER16x32 to the available font names
MAINTAINERS: fpga: hand off maintainership to Moritz
treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 507
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KVM: arm/arm64: Fix emulated ptimer irq injection
net: dsa: mv88e6xxx: fix shift of FID bits in mv88e6185_g1_vtu_loadpurge()
tests: kvm: Check for a kernel warning
kvm: tests: Sort tests in the Makefile alphabetically
KVM: x86/mmu: Allocate PAE root array when using SVM's 32-bit NPT
KVM: x86: Modify struct kvm_nested_state to have explicit fields for data
fanotify: update connector fsid cache on add mark
quota: fix a problem about transfer quota
drm/i915: Don't clobber M/N values during fastset check
powerpc: enable a 30-bit ZONE_DMA for 32-bit pmac
ovl: make i_ino consistent with st_ino in more cases
scsi: qla2xxx: Fix hardlockup in abort command during driver remove
scsi: ufs: Avoid runtime suspend possibly being blocked forever
scsi: qedi: update driver version to 8.37.0.20
scsi: qedi: Check targetname while finding boot target information
hvsock: fix epollout hang from race condition
net/udp_gso: Allow TX timestamp with UDP GSO
net: netem: fix use after free and double free with packet corruption
net: netem: fix backlog accounting for corrupted GSO frames
net: lio_core: fix potential sign-extension overflow on large shift
tipc: pass tunnel dev as NULL to udp_tunnel(6)_xmit_skb
ip6_tunnel: allow not to count pkts on tstats by passing dev as NULL
ip_tunnel: allow not to count pkts on tstats by setting skb's dev to NULL
apparmor: reset pos on failure to unpack for various functions
apparmor: enforce nullbyte at end of tag string
apparmor: fix PROFILE_MEDIATES for untrusted input
RDMA/efa: Handle mmap insertions overflow
tun: wake up waitqueues after IFF_UP is set
drm: return -EFAULT if copy_to_user() fails
net: remove duplicate fetch in sock_getsockopt
tipc: fix issues with early FAILOVER_MSG from peer
bnx2x: Check if transceiver implements DDM before access
xhci: detect USB 3.2 capable host controllers correctly
usb: xhci: Don't try to recover an endpoint if port is in error state.
KVM: fix typo in documentation
drm/panfrost: Make sure a BO is only unmapped when appropriate
md: fix for divide error in status_resync
soc: ixp4xx: npe: Fix an IS_ERR() vs NULL check in probe
arm64/mm: don't initialize pgd_cache twice
MAINTAINERS: Update my email address
arm64/sve: <uapi/asm/ptrace.h> should not depend on <uapi/linux/prctl.h>
ovl: fix typo in MODULE_PARM_DESC
ovl: fix bogus -Wmaybe-unitialized warning
ovl: don't fail with disconnected lower NFS
mmc: core: Prevent processing SDIO IRQs when the card is suspended
mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning
brcmfmac: sdio: Don't tune while the card is off
mmc: core: Add sdio_retune_hold_now() and sdio_retune_release()
brcmfmac: sdio: Disable auto-tuning around commands expected to fail
mmc: core: API to temporarily disable retuning for SDIO CRC errors
Revert "brcmfmac: disable command decode in sdio_aos"
ARM: ixp4xx: include irqs.h where needed
ARM: ixp4xx: mark ixp4xx_irq_setup as __init
ARM: ixp4xx: don't select SERIAL_OF_PLATFORM
firmware: trusted_foundations: add ARMv7 dependency
usb: dwc2: Use generic PHY width in params setup
RDMA/efa: Fix success return value in case of error
IB/hfi1: Handle port down properly in pio
IB/hfi1: Handle wakeup of orphaned QPs for pio
IB/hfi1: Wakeup QPs orphaned on wait list after flush
IB/hfi1: Use aborts to trigger RC throttling
IB/hfi1: Create inline to get extended headers
IB/hfi1: Silence txreq allocation warnings
IB/hfi1: Avoid hardlockup with flushlist_lock
KVM: PPC: Book3S HV: Only write DAWR[X] when handling h_set_dawr in real mode
KVM: PPC: Book3S HV: Fix r3 corruption in h_set_dabr()
fs/namespace: fix unprivileged mount propagation
vfs: fsmount: add missing mntget()
cifs: fix GlobalMid_Lock bug in cifs_reconnect
SMB3: retry on STATUS_INSUFFICIENT_RESOURCES instead of failing write
staging: erofs: add requirements field in superblock
arm64: ssbd: explicitly depend on <linux/prctl.h>
block: fix page leak when merging to same page
block: return from __bio_try_merge_page if merging occured in the same page
Btrfs: fix failure to persist compression property xattr deletion on fsync
riscv: remove unused barrier defines
usb: chipidea: udc: workaround for endpoint conflict issue
MAINTAINERS: Change QCOM repo location
mmc: mediatek: fix SDIO IRQ detection issue
mmc: mediatek: fix SDIO IRQ interrupt handle flow
mmc: core: complete HS400 before checking status
riscv: mm: synchronize MMU after pte change
MAINTAINERS: Update my email address to use @kernel.org
ANDROID: update abi_gki_aarch64.xml for 5.2-rc5
riscv: dts: add initial board data for the SiFive HiFive Unleashed
riscv: dts: add initial support for the SiFive FU540-C000 SoC
dt-bindings: riscv: convert cpu binding to json-schema
dt-bindings: riscv: sifive: add YAML documentation for the SiFive FU540
arch: riscv: add support for building DTB files from DT source data
drm/i915/gvt: ignore unexpected pvinfo write
lapb: fixed leak of control-blocks.
tipc: purge deferredq list for each grp member in tipc_group_delete
ax25: fix inconsistent lock state in ax25_destroy_timer
neigh: fix use-after-free read in pneigh_get_next
tcp: fix compile error if !CONFIG_SYSCTL
hv_sock: Suppress bogus "may be used uninitialized" warnings
be2net: Fix number of Rx queues used for flow hashing
net: handle 802.1P vlan 0 packets properly
Linux 5.2-rc5
tcp: enforce tcp_min_snd_mss in tcp_mtu_probing()
tcp: add tcp_min_snd_mss sysctl
tcp: tcp_fragment() should apply sane memory limits
tcp: limit payload size of sacked skbs
Revert "net: phylink: set the autoneg state in phylink_phy_change"
bpf: fix nested bpf tracepoints with per-cpu data
bpf: Fix out of bounds memory access in bpf_sk_storage
vsock/virtio: set SOCK_DONE on peer shutdown
net: dsa: rtl8366: Fix up VLAN filtering
net: phylink: set the autoneg state in phylink_phy_change
powerpc/32: fix build failure on book3e with KVM
powerpc/booke: fix fast syscall entry on SMP
powerpc/32s: fix initial setup of segment registers on secondary CPU
x86/microcode, cpuhotplug: Add a microcode loader CPU hotplug callback
net: add high_order_alloc_disable sysctl/static key
tcp: add tcp_tx_skb_cache sysctl
tcp: add tcp_rx_skb_cache sysctl
sysctl: define proc_do_static_key()
hv_netvsc: Set probe mode to sync
net: sched: flower: don't call synchronize_rcu() on mask creation
net: dsa: fix warning same module names
sctp: Free cookie before we memdup a new one
net: dsa: microchip: Don't try to read stats for unused ports
qmi_wwan: extend permitted QMAP mux_id value range
qmi_wwan: avoid RCU stalls on device disconnect when in QMAP mode
qmi_wwan: add network device usage statistics for qmimux devices
qmi_wwan: add support for QMAP padding in the RX path
bpf, x64: fix stack layout of JITed bpf code
Smack: Restore the smackfsdef mount option and add missing prefixes
bpf, devmap: Add missing RCU read lock on flush
bpf, devmap: Add missing bulk queue free
bpf, devmap: Fix premature entry free on destroying map
ftrace: Fix NULL pointer dereference in free_ftrace_func_mapper()
module: Fix livepatch/ftrace module text permissions race
tracing/uprobe: Fix obsolete comment on trace_uprobe_create()
tracing/uprobe: Fix NULL pointer dereference in trace_uprobe_create()
tracing: Make two symbols static
tracing: avoid build warning with HAVE_NOP_MCOUNT
tracing: Fix out-of-range read in trace_stack_print()
gfs2: Fix rounding error in gfs2_iomap_page_prepare
net: phylink: further mac_config documentation improvements
nfc: Ensure presence of required attributes in the deactivate_target handler
btrfs: start readahead also in seed devices
x86/kasan: Fix boot with 5-level paging and KASAN
cfg80211: report measurement start TSF correctly
cfg80211: fix memory leak of wiphy device name
cfg80211: util: fix bit count off by one
mac80211: do not start any work during reconfigure flow
cfg80211: use BIT_ULL in cfg80211_parse_mbssid_data()
mac80211: only warn once on chanctx_conf being NULL
mac80211: drop robust management frames from unknown TA
gpu: ipu-v3: image-convert: Fix image downsize coefficients
gpu: ipu-v3: image-convert: Fix input bytesperline for packed formats
gpu: ipu-v3: image-convert: Fix input bytesperline width/height align
thunderbolt: Implement CIO reset correctly for Titan Ridge
ARM: davinci: da8xx: specify dma_coherent_mask for lcdc
ARM: davinci: da850-evm: call regulator_has_full_constraints()
timekeeping: Repair ktime_get_coarse*() granularity
Revert "ALSA: hda/realtek - Improve the headset mic for Acer Aspire laptops"
ANDROID: update abi_gki_aarch64.xml
mm/devm_memremap_pages: fix final page put race
PCI/P2PDMA: track pgmap references per resource, not globally
lib/genalloc: introduce chunk owners
PCI/P2PDMA: fix the gen_pool_add_virt() failure path
mm/devm_memremap_pages: introduce devm_memunmap_pages
drivers/base/devres: introduce devm_release_action()
mm/vmscan.c: fix trying to reclaim unevictable LRU page
coredump: fix race condition between collapse_huge_page() and core dumping
mm/mlock.c: change count_mm_mlocked_page_nr return type
mm: mmu_gather: remove __tlb_reset_range() for force flush
fs/ocfs2: fix race in ocfs2_dentry_attach_lock()
mm/vmscan.c: fix recent_rotated history
mm/mlock.c: mlockall error for flag MCL_ONFAULT
scripts/decode_stacktrace.sh: prefix addr2line with $CROSS_COMPILE
mm/list_lru.c: fix memory leak in __memcg_init_list_lru_node
mm: memcontrol: don't batch updates of local VM stats and events
PCI: PM: Skip devices in D0 for suspend-to-idle
ANDROID: Removed extraneous configs from gki
powerpc/bpf: use unsigned division instruction for 64-bit operations
bpf: fix div64 overflow tests to properly detect errors
bpf: sync BPF_FIB_LOOKUP flag changes with BPF uapi
bpf: simplify definition of BPF_FIB_LOOKUP related flags
cifs: add spinlock for the openFileList to cifsInodeInfo
cifs: fix panic in smb2_reconnect
x86/fpu: Don't use current->mm to check for a kthread
KVM: nVMX: use correct clean fields when copying from eVMCS
vfio-ccw: Destroy kmem cache region on module exit
block/ps3vram: Use %llu to format sector_t after LBDAF removal
libata: Extend quirks for the ST1000LM024 drives with NOLPM quirk
bcache: only set BCACHE_DEV_WB_RUNNING when cached device attached
bcache: fix stack corruption by PRECEDING_KEY()
arm64/sve: Fix missing SVE/FPSIMD endianness conversions
blk-mq: remove WARN_ON(!q->elevator) from blk_mq_sched_free_requests
blkio-controller.txt: Remove references to CFQ
block/switching-sched.txt: Update to blk-mq schedulers
null_blk: remove duplicate check for report zone
blk-mq: no need to check return value of debugfs_create functions
io_uring: fix memory leak of UNIX domain socket inode
block: force select mq-deadline for zoned block devices
binder: fix possible UAF when freeing buffer
drm/amdgpu: return 0 by default in amdgpu_pm_load_smu_firmware
drm/amdgpu: Fix bounds checking in amdgpu_ras_is_supported()
ANDROID: x86 gki_defconfig: enable DMA_CMA
ANDROID: Fixed x86 regression
ANDROID: gki_defconfig: enable DMA_CMA
Input: synaptics - enable SMBus on ThinkPad E480 and E580
net: mvpp2: prs: Use the correct helpers when removing all VID filters
net: mvpp2: prs: Fix parser range for VID filtering
mlxsw: spectrum: Disallow prio-tagged packets when PVID is removed
mlxsw: spectrum_buffers: Reduce pool size on Spectrum-2
selftests: tc_flower: Add TOS matching test
mlxsw: spectrum_flower: Fix TOS matching
selftests: mlxsw: Test nexthop offload indication
mlxsw: spectrum_router: Refresh nexthop neighbour when it becomes dead
mlxsw: spectrum: Use different seeds for ECMP and LAG hash
net: tls, correctly account for copied bytes with multiple sk_msgs
vrf: Increment Icmp6InMsgs on the original netdev
cpuset: restore sanity to cpuset_cpus_allowed_fallback()
net: ethtool: Allow matching on vlan DEI bit
linux-next: DOC: RDS: Fix a typo in rds.txt
x86/kgdb: Return 0 from kgdb_arch_set_breakpoint()
mpls: fix af_mpls dependencies for real
selinux: fix a missing-check bug in selinux_sb_eat_lsm_opts()
selinux: fix a missing-check bug in selinux_add_mnt_opt( )
arm64: tlbflush: Ensure start/end of address range are aligned to stride
usb: typec: Make sure an alt mode exist before getting its partner
KVM: arm/arm64: vgic: Fix kvm_device leak in vgic_its_destroy
KVM: arm64: Filter out invalid core register IDs in KVM_GET_REG_LIST
KVM: arm64: Implement vq_present() as a macro
xdp: check device pointer before clearing
bpf: net: Set sk_bpf_storage back to NULL for cloned sk
Btrfs: fix race between block group removal and block group allocation
clocksource/drivers/arm_arch_timer: Don't trace count reader functions
i2c: pca-platform: Fix GPIO lookup code
thunderbolt: Make sure device runtime resume completes before taking domain lock
drm: add fallback override/firmware EDID modes workaround
i2c: acorn: fix i2c warning
arm64: Don't unconditionally add -Wno-psabi to KBUILD_CFLAGS
drm/edid: abstract override/firmware EDID retrieval
platform/mellanox: mlxreg-hotplug: Add devm_free_irq call to remove flow
platform/x86: mlx-platform: Fix parent device in i2c-mux-reg device registration
platform/x86: intel-vbtn: Report switch events when event wakes device
platform/x86: asus-wmi: Only Tell EC the OS will handle display hotkeys from asus_nb_wmi
ARM: mvebu_v7_defconfig: fix Ethernet on Clearfog
x86/resctrl: Prevent NULL pointer dereference when local MBM is disabled
x86/resctrl: Don't stop walking closids when a locksetup group is found
iommu/arm-smmu: Avoid constant zero in TLBI writes
drm/i915/perf: fix whitelist on Gen10+
drm/i915/sdvo: Implement proper HDMI audio support for SDVO
drm/i915: Fix per-pixel alpha with CCS
drm/i915/dmc: protect against reading random memory
drm/i915/dsi: Use a fuzzy check for burst mode clock check
Input: imx_keypad - make sure keyboard can always wake up system
selinux: log raw contexts as untrusted strings
ptrace: restore smp_rmb() in __ptrace_may_access()
IB/hfi1: Correct tid qp rcd to match verbs context
IB/hfi1: Close PSM sdma_progress sleep window
IB/hfi1: Validate fault injection opcode user input
geneve: Don't assume linear buffers in error handler
vxlan: Don't assume linear buffers in error handler
net: openvswitch: do not free vport if register_netdevice() is failed.
net: correct udp zerocopy refcnt also when zerocopy only on append
drm/amdgpu/{uvd,vcn}: fetch ring's read_ptr after alloc
ovl: fix wrong flags check in FS_IOC_FS[SG]ETXATTR ioctls
riscv: Fix udelay in RV32.
drm/vmwgfx: fix a warning due to missing dma_parms
riscv: export pm_power_off again
drm/vmwgfx: Honor the sg list segment size limitation
RISC-V: defconfig: enable clocks, serial console
drm/vmwgfx: Use the backdoor port if the HB port is not available
bpf: lpm_trie: check left child of last leftmost node for NULL
Revert "fuse: require /dev/fuse reads to have enough buffer capacity"
ALSA: ice1712: Check correct return value to snd_i2c_sendbytes (EWS/DMX 6Fire)
ALSA: oxfw: allow PCM capture for Stanton SCS.1m
ALSA: firewire-motu: fix destruction of data for isochronous resources
s390/ctl_reg: mark __ctl_set_bit and __ctl_clear_bit as __always_inline
s390/boot: disable address-of-packed-member warning
ANDROID: update gki aarch64 ABI representation
cgroup: Fix css_task_iter_advance_css_set() cset skip condition
drm/panfrost: Require the simple_ondemand governor
drm/panfrost: make devfreq optional again
drm/gem_shmem: Use a writecombine mapping for ->vaddr
mmc: sdhi: disallow HS400 for M3-W ES1.2, RZ/G2M, and V3H
ASoC: Intel: sst: fix kmalloc call with wrong flags
ASoC: core: Fix deadlock in snd_soc_instantiate_card()
cgroup/bfq: revert bfq.weight symlink change
ARM: dts: am335x phytec boards: Fix cd-gpios active level
ARM: dts: dra72x: Disable usb4_tm target module
nfp: ensure skb network header is set for packet redirect
tcp: fix undo spurious SYNACK in passive Fast Open
mpls: fix af_mpls dependencies
ibmvnic: Fix unchecked return codes of memory allocations
ibmvnic: Refresh device multicast list after reset
ibmvnic: Do not close unopened driver during reset
mpls: fix warning with multi-label encap
net: phy: rename Asix Electronics PHY driver
ipv6: flowlabel: fl6_sock_lookup() must use atomic_inc_not_zero
net: ipv4: fib_semantics: fix uninitialized variable
Input: iqs5xx - get axis info before calling input_mt_init_slots()
Linux 5.2-rc4
drm: panel-orientation-quirks: Add quirk for GPD MicroPC
drm: panel-orientation-quirks: Add quirk for GPD pocket2
counter/ftm-quaddec: Add missing dependencies in Kconfig
staging: iio: adt7316: Fix build errors when GPIOLIB is not set
x86/fpu: Update kernel's FPU state before using for the fsave header
MAINTAINERS: Karthikeyan Ramasubramanian is MIA
i2c: xiic: Add max_read_len quirk
ANDROID: update ABI representation
gpio: pca953x: hack to fix 24 bit gpio expanders
net/mlx5e: Support tagged tunnel over bond
net/mlx5e: Avoid detaching non-existing netdev under switchdev mode
net/mlx5e: Fix source port matching in fdb peer flow rule
net/mlx5e: Replace reciprocal_scale in TX select queue function
net/mlx5e: Add ndo_set_feature for uplink representor
net/mlx5: Avoid reloading already removed devices
net/mlx5: Update pci error handler entries and command translation
RAS/CEC: Convert the timer callback to a workqueue
RAS/CEC: Fix binary search function
x86/mm/KASLR: Compute the size of the vmemmap section properly
can: purge socket error queue on sock destruct
can: flexcan: Remove unneeded registration message
can: af_can: Fix error path of can_init()
can: m_can: implement errata "Needless activation of MRAF irq"
can: mcp251x: add support for mcp25625
dt-bindings: can: mcp251x: add mcp25625 support
can: xilinx_can: use correct bittiming_const for CAN FD core
can: flexcan: fix timeout when set small bitrate
can: usb: Kconfig: Remove duplicate menu entry
lockref: Limit number of cmpxchg loop retries
uaccess: add noop untagged_addr definition
x86/insn-eval: Fix use-after-free access to LDT entry
kbuild: use more portable 'command -v' for cc-cross-prefix
s390/unwind: correct stack switching during unwind
scsi: hpsa: correct ioaccel2 chaining
btrfs: Always trim all unallocated space in btrfs_trim_free_extents
netfilter: ipv6: nf_defrag: accept duplicate fragments again
powerpc/32s: fix booting with CONFIG_PPC_EARLY_DEBUG_BOOTX
drm/meson: fix G12A primary plane disabling
drm/meson: fix primary plane disabling
drm/meson: fix G12A HDMI PLL settings for 4K60 1000/1001 variations
block, bfq: add weight symlink to the bfq.weight cgroup parameter
cgroup: let a symlink too be created with a cftype file
powerpc/64s: __find_linux_pte() synchronization vs pmdp_invalidate()
powerpc/64s: Fix THP PMD collapse serialisation
powerpc: Fix kexec failure on book3s/32
drm/nouveau/secboot/gp10[2467]: support newer FW to fix SEC2 failures on some boards
drm/nouveau/secboot: enable loading of versioned LS PMU/SEC2 ACR msgqueue FW
drm/nouveau/secboot: split out FW version-specific LS function pointers
drm/nouveau/secboot: pass max supported FW version to LS load funcs
drm/nouveau/core: support versioned firmware loading
drm/nouveau/core: pass subdev into nvkm_firmware_get, rather than device
block: free sched's request pool in blk_cleanup_queue
bpf: expand section tests for test_section_names
bpf: more msg_name rewrite tests to test_sock_addr
bpf, bpftool: enable recvmsg attach types
bpf, libbpf: enable recvmsg attach types
bpf: sync tooling uapi header
bpf: fix unconnected udp hooks
vfio/mdev: Synchronize device create/remove with parent removal
vfio/mdev: Avoid creating sysfs remove file on stale device removal
pktgen: do not sleep with the thread lock held.
net: mvpp2: Use strscpy to handle stat strings
net: rds: fix memory leak in rds_ib_flush_mr_pool
ipv6: fix EFAULT on sendto with icmpv6 and hdrincl
ipv6: use READ_ONCE() for inet->hdrincl as in ipv4
soundwire: intel: set dai min and max channels correctly
soundwire: stream: fix bad unlock balance
x86/fpu: Use fault_in_pages_writeable() for pre-faulting
nvme-rdma: use dynamic dma mapping per command
nvme: Fix u32 overflow in the number of namespace list calculation
vfio/mdev: Improve the create/remove sequence
SoC: rt274: Fix internal jack assignment in set_jack callback
ALSA: hdac: fix memory release for SST and SOF drivers
ASoC: SOF: Intel: hda: use the defined ppcap functions
ASoC: core: move DAI pre-links initiation to snd_soc_instantiate_card
ASoC: Intel: cht_bsw_rt5672: fix kernel oops with platform_name override
ASoC: Intel: cht_bsw_nau8824: fix kernel oops with platform_name override
ASoC: Intel: bytcht_es8316: fix kernel oops with platform_name override
ASoC: Intel: cht_bsw_max98090: fix kernel oops with platform_name override
Revert "gfs2: Replace gl_revokes with a GLF flag"
arm64: Silence gcc warnings about arch ABI drift
parisc: Fix crash due alternative coding for NP iopdir_fdc bit
parisc: Use lpa instruction to load physical addresses in driver code
parisc: configs: Remove useless UEVENT_HELPER_PATH
parisc: Use implicit space register selection for loading the coherence index of I/O pdirs
usb: gadget: udc: lpc32xx: fix return value check in lpc32xx_udc_probe()
usb: gadget: dwc2: fix zlp handling
usb: dwc2: Set actual frame number for completed ISOC transfer for none DDMA
usb: gadget: udc: lpc32xx: allocate descriptor with GFP_ATOMIC
usb: gadget: fusb300_udc: Fix memory leak of fusb300->ep[i]
usb: phy: mxs: Disable external charger detect in mxs_phy_hw_init()
usb: dwc2: Fix DMA cache alignment issues
usb: dwc2: host: Fix wMaxPacketSize handling (fix webcam regression)
ARM64: trivial: s/TIF_SECOMP/TIF_SECCOMP/ comment typo fix
drm/komeda: Potential error pointer dereference
drm/komeda: remove set but not used variable 'kcrtc'
x86/CPU: Add more Icelake model numbers
hwmon: (pmbus/core) Treat parameters as paged if on multiple pages
hwmon: (pmbus/core) mutex_lock write in pmbus_set_samples
hwmon: (core) add thermal sensors only if dev->of_node is present
Revert "fib_rules: return 0 directly if an exactly same rule exists when NLM_F_EXCL not supplied"
net: aquantia: fix wol configuration not applied sometimes
ethtool: fix potential userspace buffer overflow
Fix memory leak in sctp_process_init
net: rds: fix memory leak when unload rds_rdma
ipv6: fix the check before getting the cookie in rt6_get_cookie
ipv4: not do cache for local delivery if bc_forwarding is enabled
selftests: vm: Fix test build failure when built by itself
tools: bpftool: Fix JSON output when lookup fails
mmc: also set max_segment_size in the device
mtip32xx: also set max_segment_size in the device
rsxx: don't call dma_set_max_seg_size
nvme-pci: don't limit DMA segement size
s390/qeth: handle error when updating TX queue count
s390/qeth: fix VLAN attribute in bridge_hostnotify udev event
s390/qeth: check dst entry before use
s390/qeth: handle limited IPv4 broadcast in L3 TX path
ceph: fix error handling in ceph_get_caps()
ceph: avoid iput_final() while holding mutex or in dispatch thread
ceph: single workqueue for inode related works
cgroup: css_task_iter_skip()'d iterators must be advanced before accessed
drm/amd/amdgpu: add RLC firmware to support raven1 refresh
drm/amd/powerplay: add set_power_profile_mode for raven1_refresh
drm/amdgpu: fix ring test failure issue during s3 in vce 3.0 (V2)
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lib/test_stackinit: Handle Clang auto-initialization pattern
block: Drop unlikely before IS_ERR(_OR_NULL)
xen/swiotlb: don't initialize swiotlb twice on arm64
s390/mm: fix address space detection in exception handling
HID: logitech-dj: Fix 064d:c52f receiver support
Revert "HID: core: Call request_module before doing device_add"
Revert "HID: core: Do not call request_module() in async context"
Revert "HID: Increase maximum report size allowed by hid_field_extract()"
tests: fix pidfd-test compilation
signal: improve comments
samples: fix pidfd-metadata compilation
arm64: arch_timer: mark functions as __always_inline
arm64: smp: Moved cpu_logical_map[] to smp.h
arm64: cpufeature: Fix missing ZFR0 in __read_sysreg_by_encoding()
selftests/bpf: move test_lirc_mode2_user to TEST_GEN_PROGS_EXTENDED
USB: Fix chipmunk-like voice when using Logitech C270 for recording audio.
USB: usb-storage: Add new ID to ums-realtek
udmabuf: actually unmap the scatterlist
net: fix indirect calls helpers for ptype list hooks.
net: ipvlan: Fix ipvlan device tso disabled while NETIF_F_IP_CSUM is set
scsi: smartpqi: unlock on error in pqi_submit_raid_request_synchronous()
scsi: ufs: Check that space was properly alloced in copy_query_response
udp: only choose unbound UDP socket for multicast when not in a VRF
net/tls: replace the sleeping lock around RX resync with a bit lock
Revert "net/tls: avoid NULL-deref on resync during device removal"
block: aoe: no need to check return value of debugfs_create functions
net: dsa: sja1105: Fix link speed not working at 100 Mbps and below
net: phylink: avoid reducing support mask
scripts/checkstack.pl: Fix arm64 wrong or unknown architecture
kbuild: tar-pkg: enable communication with jobserver
kconfig: tests: fix recursive inclusion unit test
kbuild: teach kselftest-merge to find nested config files
nvmet: fix data_len to 0 for bdev-backed write_zeroes
MAINTAINERS: Hand over skd maintainership
ASoC: sun4i-i2s: Add offset to RX channel select
ASoC: sun4i-i2s: Fix sun8i tx channel offset mask
ASoC: max98090: remove 24-bit format support if RJ is 0
ASoC: da7219: Fix build error without CONFIG_I2C
ASoC: SOF: Intel: hda: Fix COMPILE_TEST build error
drm/arm/hdlcd: Allow a bit of clock tolerance
drm/arm/hdlcd: Actually validate CRTC modes
drm/arm/mali-dp: Add a loop around the second set CVAL and try 5 times
drm/komeda: fixing of DMA mapping sg segment warning
netfilter: ipv6: nf_defrag: fix leakage of unqueued fragments
habanalabs: Read upper bits of trace buffer from RWPHI
arm64: arch_k3: Fix kconfig dependency warning
drm: don't block fb changes for async plane updates
drm/vc4: fix fb references in async update
drm/msm: fix fb references in async update
drm/amd: fix fb references in async update
drm/rockchip: fix fb references in async update
xen-blkfront: switch kcalloc to kvcalloc for large array allocation
drm/mediatek: call mtk_dsi_stop() after mtk_drm_crtc_atomic_disable()
drm/mediatek: clear num_pipes when unbind driver
drm/mediatek: call drm_atomic_helper_shutdown() when unbinding driver
drm/mediatek: unbind components in mtk_drm_unbind()
drm/mediatek: fix unbind functions
net: sfp: read eeprom in maximum 16 byte increments
selftests: set sysctl bc_forwarding properly in router_broadcast.sh
ANDROID: update gki aarch64 ABI representation
net: ethernet: mediatek: Use NET_IP_ALIGN to judge if HW RX_2BYTE_OFFSET is enabled
net: ethernet: mediatek: Use hw_feature to judge if HWLRO is supported
net: ethernet: ti: cpsw_ethtool: fix ethtool ring param set
ANDROID: gki_defconfig: Enable CMA, SLAB_FREELIST (RANDOM and HARDENED) on x86
bpf: udp: Avoid calling reuseport's bpf_prog from udp_gro
bpf: udp: ipv6: Avoid running reuseport's bpf_prog from __udp6_lib_err
rcu: locking and unlocking need to always be at least barriers
ANDROID: gki_defconfig: enable SLAB_FREELIST_RANDOM, SLAB_FREELIST_HARDENED
ANDROID: gki_defconfig: enable CMA and increase CMA_AREAS
ASoC: SOF: fix DSP oops definitions in FW ABI
ASoC: hda: fix unbalanced codec dev refcount for HDA_DEV_ASOC
ASoC: SOF: ipc: replace fw ready bitfield with explicit bit ordering
ASoC: SOF: bump to ABI 3.6
ASoC: SOF: soundwire: add initial soundwire support
ASoC: SOF: uapi: mirror firmware changes
ASoC: Intel: Baytrail: add quirk for Aegex 10 (RU2) tablet
xfs: inode btree scrubber should calculate im_boffset correctly
mmc: sdhci_am654: Fix SLOTTYPE write
usb: typec: ucsi: ccg: fix memory leak in do_flash
ANDROID: update gki aarch64 ABI representation
habanalabs: Fix virtual address access via debugfs for 2MB pages
drm/komeda: Constify the usage of komeda_component/pipeline/dev_funcs
x86/power: Fix 'nosmt' vs hibernation triple fault during resume
mm/vmalloc: Avoid rare case of flushing TLB with weird arguments
mm/vmalloc: Fix calculation of direct map addr range
PM: sleep: Add kerneldoc comments to some functions
drm/i915/gvt: save RING_HEAD into vreg when vgpu switched out
sparc: perf: fix updated event period in response to PERF_EVENT_IOC_PERIOD
mdesc: fix a missing-check bug in get_vdev_port_node_info()
drm/i915/gvt: add F_CMD_ACCESS flag for wa regs
sparc64: Fix regression in non-hypervisor TLB flush xcall
packet: unconditionally free po->rollover
Update my email address
net: hns: Fix loopback test failed at copper ports
Linux 5.2-rc3
net: dsa: mv88e6xxx: avoid error message on remove from VLAN 0
mm, compaction: make sure we isolate a valid PFN
include/linux/generic-radix-tree.h: fix kerneldoc comment
kernel/signal.c: trace_signal_deliver when signal_group_exit
drivers/iommu/intel-iommu.c: fix variable 'iommu' set but not used
spdxcheck.py: fix directory structures
kasan: initialize tag to 0xff in __kasan_kmalloc
z3fold: fix sheduling while atomic
scripts/gdb: fix invocation when CONFIG_COMMON_CLK is not set
mm/gup: continue VM_FAULT_RETRY processing even for pre-faults
ocfs2: fix error path kobject memory leak
memcg: make it work on sparse non-0-node systems
mm, memcg: consider subtrees in memory.events
prctl_set_mm: downgrade mmap_sem to read lock
prctl_set_mm: refactor checks from validate_prctl_map
kernel/fork.c: make max_threads symbol static
arch/arm/boot/compressed/decompress.c: fix build error due to lz4 changes
arch/parisc/configs/c8000_defconfig: remove obsoleted CONFIG_DEBUG_SLAB_LEAK
mm/vmalloc.c: fix typo in comment
lib/sort.c: fix kernel-doc notation warnings
mm: fix Documentation/vm/hmm.rst Sphinx warnings
treewide: fix typos of SPDX-License-Identifier
crypto: ux500 - fix license comment syntax error
MAINTAINERS: add I2C DT bindings to ARM platforms
MAINTAINERS: add DT bindings to i2c drivers
mwifiex: Fix heap overflow in mwifiex_uap_parse_tail_ies()
iwlwifi: mvm: change TLC config cmd sent by rs to be async
iwlwifi: Fix double-free problems in iwl_req_fw_callback()
iwlwifi: fix AX201 killer sku loading firmware issue
iwlwifi: print fseq info upon fw assert
iwlwifi: clear persistence bit according to device family
iwlwifi: fix load in rfkill flow for unified firmware
iwlwifi: mvm: remove d3_sram debugfs file
bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh
libbpf: Return btf_fd for load_sk_storage_btf
HID: a4tech: fix horizontal scrolling
HID: hyperv: Add a module description line
net: dsa: sja1105: Don't store frame type in skb->cb
block: print offending values when cloned rq limits are exceeded
blk-mq: Document the blk_mq_hw_queue_to_node() arguments
blk-mq: Fix spelling in a source code comment
block: Fix bsg_setup_queue() kernel-doc header
block: Fix rq_qos_wait() kernel-doc header
block: Fix blk_mq_*_map_queues() kernel-doc headers
block: Fix throtl_pending_timer_fn() kernel-doc header
block: Convert blk_invalidate_devt() header into a non-kernel-doc header
block/partitions/ldm: Convert a kernel-doc header into a non-kernel-doc header
leds: avoid flush_work in atomic context
cgroup: Include dying leaders with live threads in PROCS iterations
cgroup: Implement css_task_iter_skip()
cgroup: Call cgroup_release() before __exit_signal()
netfilter: nf_tables: fix module autoload with inet family
Revert "lockd: Show pid of lockd for remote locks"
ALSA: hda/realtek - Update headset mode for ALC256
fs/adfs: fix filename fixup handling for "/" and "//" names
fs/adfs: move append_filetype_suffix() into adfs_object_fixup()
fs/adfs: remove truncated filename hashing
fs/adfs: factor out filename fixup
fs/adfs: factor out object fixups
fs/adfs: factor out filename case lowering
fs/adfs: factor out filename comparison
ovl: doc: add non-standard corner cases
pstore/ram: Run without kernel crash dump region
MAINTAINERS: add Vasily Gorbik and Christian Borntraeger for s390
MAINTAINERS: Farewell Martin Schwidefsky
pstore: Set tfm to NULL on free_buf_for_compression
nds32: add new emulations for floating point instruction
nds32: Avoid IEX status being incorrectly modified
math-emu: Use statement expressions to fix Wshift-count-overflow warning
net: correct zerocopy refcnt with udp MSG_MORE
ethtool: Check for vlan etype or vlan tci when parsing flow_rule
net: don't clear sock->sk early to avoid trouble in strparser
net-gro: fix use-after-free read in napi_gro_frags()
net: dsa: tag_8021q: Create a stable binary format
net: dsa: tag_8021q: Change order of rx_vid setup
net: mvpp2: fix bad MVPP2_TXQ_SCHED_TOKEN_CNTR_REG queue value
docs cgroups: add another example size for hugetlb
NFSv4.1: Fix bug only first CB_NOTIFY_LOCK is handled
NFSv4.1: Again fix a race where CB_NOTIFY_LOCK fails to wake a waiter
ipv4: tcp_input: fix stack out of bounds when parsing TCP options.
mlxsw: spectrum: Prevent force of 56G
mlxsw: spectrum_acl: Avoid warning after identical rules insertion
SUNRPC: Fix a use after free when a server rejects the RPCSEC_GSS credential
net: dsa: mv88e6xxx: fix handling of upper half of STATS_TYPE_PORT
SUNRPC fix regression in umount of a secure mount
r8169: fix MAC address being lost in PCI D3
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net: core: support XDP generic on stacked devices.
netvsc: unshare skb in VF rx handler
udp: Avoid post-GRO UDP checksum recalculation
nvme-tcp: fix queue mapping when queue count is limited
nvme-rdma: fix queue mapping when queue count is limited
fpga: zynqmp-fpga: Correctly handle error pointer
selftests: vm: install test_vmalloc.sh for run_vmtests
userfaultfd: selftest: fix compiler warning
kselftest/cgroup: fix incorrect test_core skip
kselftest/cgroup: fix unexpected testing failure on test_core
kselftest/cgroup: fix unexpected testing failure on test_memcontrol
xtensa: Fix section mismatch between memblock_reserve and mem_reserve
signal/ptrace: Don't leak unitialized kernel memory with PTRACE_PEEK_SIGINFO
mwifiex: Abort at too short BSS descriptor element
mwifiex: Fix possible buffer overflows at parsing bss descriptor
drm/i915/gvt: Assign NULL to the pointer after memory free.
drm/i915/gvt: Check if cur_pt_type is valid
x86: intel_epb: Do not build when CONFIG_PM is unset
crypto: hmac - fix memory leak in hmac_init_tfm()
crypto: jitterentropy - change back to module_init()
ARM: dts: Drop bogus CLKSEL for timer12 on dra7
KVM: PPC: Book3S HV: Restore SPRG3 in kvmhv_p9_guest_entry()
KVM: PPC: Book3S HV: Fix lockdep warning when entering guest on POWER9
KVM: PPC: Book3S HV: XIVE: Fix page offset when clearing ESB pages
KVM: PPC: Book3S HV: XIVE: Take the srcu read lock when accessing memslots
KVM: PPC: Book3S HV: XIVE: Do not clear IRQ data of passthrough interrupts
KVM: PPC: Book3S HV: XIVE: Introduce a new mutex for the XIVE device
drm/i915/gvt: Fix cmd length of VEB_DI_IECP
drm/i915/gvt: refine ggtt range validation
drm/i915/gvt: Fix vGPU CSFE_CHICKEN1_REG mmio handler
drm/i915/gvt: Fix GFX_MODE handling
drm/i915/gvt: Update force-to-nonpriv register whitelist
drm/i915/gvt: Initialize intel_gvt_gtt_entry in stack
ima: show rules with IMA_INMASK correctly
evm: check hash algorithm passed to init_desc()
scsi: libsas: delete sas port if expander discover failed
scsi: libsas: only clear phy->in_shutdown after shutdown event done
scsi: scsi_dh_alua: Fix possible null-ptr-deref
scsi: smartpqi: properly set both the DMA mask and the coherent DMA mask
scsi: zfcp: fix to prevent port_remove with pure auto scan LUNs (only sdevs)
scsi: zfcp: fix missing zfcp_port reference put on -EBUSY from port_remove
scsi: libcxgbi: add a check for NULL pointer in cxgbi_check_route()
net: phy: dp83867: Set up RGMII TX delay
net: phy: dp83867: do not call config_init twice
net: phy: dp83867: increase SGMII autoneg timer duration
net: phy: dp83867: fix speed 10 in sgmii mode
net: phy: marvell10g: report if the PHY fails to boot firmware
net: phylink: ensure consistent phy interface mode
cgroup: Use css_tryget() instead of css_tryget_online() in task_get_css()
blk-mq: Fix memory leak in error handling
usbip: usbip_host: fix stub_dev lock context imbalance regression
net: sh_eth: fix mdio access in sh_eth_close() for R-Car Gen2 and RZ/A1 SoCs
MIPS: uprobes: remove set but not used variable 'epc'
s390/crypto: fix possible sleep during spinlock aquired
MIPS: pistachio: Build uImage.gz by default
MIPS: Make virt_addr_valid() return bool
MIPS: Bounds check virt_addr_valid
CIFS: cifs_read_allocate_pages: don't iterate through whole page array on ENOMEM
RDMA/efa: Remove MAYEXEC flag check from mmap flow
mlx5: avoid 64-bit division
IB/hfi1: Validate page aligned for a given virtual address
IB/{qib, hfi1, rdmavt}: Correct ibv_devinfo max_mr value
IB/hfi1: Insure freeze_work work_struct is canceled on shutdown
IB/rdmavt: Fix alloc_qpn() WARN_ON()
ASoC: sun4i-codec: fix first delay on Speaker
drm/amdgpu: reserve stollen vram for raven series
media: venus: hfi_parser: fix a regression in parser
selftests: bpf: fix compiler warning in flow_dissector test
arm64: use the correct function type for __arm64_sys_ni_syscall
arm64: use the correct function type in SYSCALL_DEFINE0
arm64: fix syscall_fn_t type
block: don't protect generic_make_request_checks with blk_queue_enter
block: move blk_exit_queue into __blk_release_queue
selftests: bpf: complete sub-register zero extension checks
selftests: bpf: move sub-register zero extension checks into subreg.c
ovl: detect overlapping layers
drm/i915/icl: Add WaDisableBankHangMode
ALSA: fireface: Use ULL suffixes for 64-bit constants
signal/arm64: Use force_sig not force_sig_fault for SIGKILL
nl80211: fill all policy .type entries
mac80211: free peer keys before vif down in mesh
ANDROID: ABI out: Use the extension .xml rather then .out
drm/mediatek: respect page offset for PRIME mmap calls
drm/mediatek: adjust ddp clock control flow
ALSA: hda/realtek - Improve the headset mic for Acer Aspire laptops
KVM: PPC: Book3S HV: XIVE: Fix the enforced limit on the vCPU identifier
KVM: PPC: Book3S HV: XIVE: Do not test the EQ flag validity when resetting
KVM: PPC: Book3S HV: XIVE: Clear file mapping when device is released
KVM: PPC: Book3S HV: Don't take kvm->lock around kvm_for_each_vcpu
KVM: PPC: Book3S: Use new mutex to synchronize access to rtas token list
KVM: PPC: Book3S HV: Use new mutex to synchronize MMU setup
KVM: PPC: Book3S HV: Avoid touching arch.mmu_ready in XIVE release functions
Revert "drivers: thermal: tsens: Add new operation to check if a sensor is enabled"
net/mlx5e: Disable rxhash when CQE compress is enabled
net/mlx5e: restrict the real_dev of vlan device is the same as uplink device
net/mlx5: Allocate root ns memory using kzalloc to match kfree
net/mlx5: Avoid double free in fs init error unwinding path
net/mlx5: Avoid double free of root ns in the error flow path
net/mlx5: Fix error handling in mlx5_load()
Documentation: net-sysfs: Remove duplicate PHY device documentation
llc: fix skb leak in llc_build_and_send_ui_pkt()
selftests: pmtu: Fix encapsulating device in pmtu_vti6_link_change_mtu
dfs_cache: fix a wrong use of kfree in flush_cache_ent()
fs/cifs/smb2pdu.c: fix buffer free in SMB2_ioctl_free
cifs: fix memory leak of pneg_inbuf on -EOPNOTSUPP ioctl case
xenbus: Avoid deadlock during suspend due to open transactions
xen/pvcalls: Remove set but not used variable
tracing: Avoid memory leak in predicate_parse()
habanalabs: fix bug in checking huge page optimization
mmc: sdhci: Fix SDIO IRQ thread deadlock
dpaa_eth: use only online CPU portals
net: mvneta: Fix err code path of probe
net: stmmac: Do not output error on deferred probe
Btrfs: fix race updating log root item during fsync
Btrfs: fix wrong ctime and mtime of a directory after log replay
ARC: [plat-hsdk] Get rid of inappropriate PHY settings
ARC: [plat-hsdk]: Add support of Vivante GPU
ARC: [plat-hsdk]: enable creg-gpio controller
Btrfs: fix fsync not persisting changed attributes of a directory
btrfs: qgroup: Check bg while resuming relocation to avoid NULL pointer dereference
btrfs: reloc: Also queue orphan reloc tree for cleanup to avoid BUG_ON()
Btrfs: incremental send, fix emission of invalid clone operations
Btrfs: incremental send, fix file corruption when no-holes feature is enabled
btrfs: correct zstd workspace manager lock to use spin_lock_bh()
btrfs: Ensure replaced device doesn't have pending chunk allocation
ia64: fix build errors by exporting paddr_to_nid()
ASoC: SOF: Intel: hda: fix the hda init chip
ASoC: SOF: ipc: fix a race, leading to IPC timeouts
ASoC: SOF: control: correct the copy size for bytes kcontrol put
ASoC: SOF: pcm: remove warning - initialize workqueue on open
ASoC: SOF: pcm: clear hw_params_upon_resume flag correctly
ASoC: SOF: core: fix error handling with the probe workqueue
ASoC: SOF: core: remove snd_soc_unregister_component in case of error
ASoC: SOF: core: remove DSP after unregistering machine driver
ASoC: soc-core: fixup references at soc_cleanup_card_resources()
arm64/module: revert to unsigned interpretation of ABS16/32 relocations
KVM: s390: Do not report unusabled IDs via KVM_CAP_MAX_VCPU_ID
kvm: fix compile on s390 part 2
xprtrdma: Use struct_size() in kzalloc()
tools headers UAPI: Sync kvm.h headers with the kernel sources
perf record: Fix s390 missing module symbol and warning for non-root users
perf machine: Read also the end of the kernel
perf test vmlinux-kallsyms: Ignore aliases to _etext when searching on kallsyms
perf session: Add missing swap ops for namespace events
perf namespace: Protect reading thread's namespace
tools headers UAPI: Sync drm/drm.h with the kernel
s390/crypto: fix gcm-aes-s390 selftest failures
s390/zcrypt: Fix wrong dispatching for control domain CPRBs
s390/pci: fix assignment of bus resources
s390/pci: fix struct definition for set PCI function
s390: mark __cpacf_check_opcode() and cpacf_query_func() as __always_inline
s390: add unreachable() to dump_fault_info() to fix -Wmaybe-uninitialized
tools headers UAPI: Sync drm/i915_drm.h with the kernel
tools headers UAPI: Sync linux/fs.h with the kernel
tools headers UAPI: Sync linux/sched.h with the kernel
tools arch x86: Sync asm/cpufeatures.h with the with the kernel
tools include UAPI: Update copy of files related to new fspick, fsmount, fsconfig, fsopen, move_mount and open_tree syscalls
perf arm64: Fix mksyscalltbl when system kernel headers are ahead of the kernel
perf data: Fix 'strncat may truncate' build failure with recent gcc
arm64: Fix the arm64_personality() syscall wrapper redirection
rtw88: Make some symbols static
rtw88: avoid circular locking between local->iflist_mtx and rtwdev->mutex
rsi: Properly initialize data in rsi_sdio_ta_reset
rtw88: fix unassigned rssi_level in rtw_sta_info
rtw88: fix subscript above array bounds compiler warning
fuse: extract helper for range writeback
fuse: fix copy_file_range() in the writeback case
mmc: meson-gx: fix irq ack
mmc: tmio: fix SCC error handling to avoid false positive CRC error
mmc: tegra: Fix a warning message
memstick: mspro_block: Fix an error code in mspro_block_issue_req()
mac80211: mesh: fix RCU warning
nl80211: fix station_info pertid memory leak
mac80211: Do not use stack memory with scatterlist for GMAC
ALSA: line6: Assure canceling delayed work at disconnection
configfs: Fix use-after-free when accessing sd->s_dentry
ALSA: hda - Force polling mode on CNL for fixing codec communication
i2c: synquacer: fix synquacer_i2c_doxfer() return value
i2c: mlxcpld: Fix wrong initialization order in probe
i2c: dev: fix potential memory leak in i2cdev_ioctl_rdwr
RDMA/core: Fix panic when port_data isn't initialized
RDMA/uverbs: Pass udata on uverbs error unwind
RDMA/core: Clear out the udata before error unwind
net: aquantia: tcp checksum 0xffff being handled incorrectly
net: aquantia: fix LRO with FCS error
net: aquantia: check rx csum for all packets in LRO session
net: aquantia: tx clean budget logic error
vhost: scsi: add weight support
vhost: vsock: add weight support
vhost_net: fix possible infinite loop
vhost: introduce vhost_exceeds_weight()
virtio: Fix indentation of VIRTIO_MMIO
virtio: add unlikely() to WARN_ON_ONCE()
iommu/vt-d: Set the right field for Page Walk Snoop
iommu/vt-d: Fix lock inversion between iommu->lock and device_domain_lock
iommu: Add missing new line for dma type
drm/etnaviv: lock MMU while dumping core
block: Don't revalidate bdev of hidden gendisk
loop: Don't change loop device under exclusive opener
drm/imx: ipuv3-plane: fix atomic update status query for non-plus i.MX6Q
drm/qxl: drop WARN_ONCE()
iio: temperature: mlx90632 Relax the compatibility check
iio: imu: st_lsm6dsx: fix PM support for st_lsm6dsx i2c controller
staging:iio:ad7150: fix threshold mode config bit
fuse: add FUSE_WRITE_KILL_PRIV
fuse: fallocate: fix return with locked inode
PCI: PM: Avoid possible suspend-to-idle issue
ACPI: PM: Call pm_set_suspend_via_firmware() during hibernation
ACPI/PCI: PM: Add missing wakeup.flags.valid checks
ovl: support the FS_IOC_FS[SG]ETXATTR ioctls
soundwire: stream: fix out of boundary access on port properties
net: tulip: de4x5: Drop redundant MODULE_DEVICE_TABLE()
selftests/tls: add test for sleeping even though there is data
net/tls: fix no wakeup on partial reads
selftests/tls: test for lowat overshoot with multiple records
net/tls: fix lowat calculation if some data came from previous record
dpaa2-eth: Make constant 64-bit long
dpaa2-eth: Use PTR_ERR_OR_ZERO where appropriate
dpaa2-eth: Fix potential spectre issue
bonding/802.3ad: fix slave link initialization transition states
io_uring: Fix __io_uring_register() false success
net: ethtool: Document get_rxfh_context and set_rxfh_context ethtool ops
net: stmmac: dwmac-mediatek: modify csr_clk value to fix mdio read/write fail
net: stmmac: fix csr_clk can't be zero issue
net: stmmac: update rx tail pointer register to fix rx dma hang issue.
ip_sockglue: Fix missing-check bug in ip_ra_control()
ipv6_sockglue: Fix a missing-check bug in ip6_ra_control()
efi: Allow the number of EFI configuration tables entries to be zero
efi/x86/Add missing error handling to old_memmap 1:1 mapping code
parisc: Fix compiler warnings in float emulation code
parisc/slab: cleanup after /proc/slab_allocators removal
bpf: sockmap, fix use after free from sleep in psock backlog workqueue
net: sched: don't use tc_action->order during action dump
cxgb4: Revert "cxgb4: Remove SGE_HOST_PAGE_SIZE dependency on page size"
net: fec: fix the clk mismatch in failed_reset path
habanalabs: Avoid using a non-initialized MMU cache mutex
habanalabs: fix debugfs code
uapi/habanalabs: add opcode for enable/disable device debug mode
habanalabs: halt debug engines on user process close
selftests: rtc: rtctest: specify timeouts
selftests/harness: Allow test to configure timeout
selftests/ftrace: Add checkbashisms meta-testcase
selftests/ftrace: Make a script checkbashisms clean
media: smsusb: better handle optional alignment
test_firmware: Use correct snprintf() limit
genwqe: Prevent an integer overflow in the ioctl
parport: Fix mem leak in parport_register_dev_model
fpga: dfl: expand minor range when registering chrdev region
fpga: dfl: Add lockdep classes for pdata->lock
fpga: dfl: afu: Pass the correct device to dma_mapping_error()
fpga: stratix10-soc: fix use-after-free on s10_init()
w1: ds2408: Fix typo after 49695ac468
(reset on output_write retry with readback)
kheaders: Do not regenerate archive if config is not changed
kheaders: Move from proc to sysfs
drm/amd/display: Don't load DMCU for Raven 1 (v2)
drm/i915: Maintain consistent documentation subsection ordering
scripts/sphinx-pre-install: make it handle Sphinx versions
docs: Fix conf.py for Sphinx 2.0
vt/fbcon: deinitialize resources in visual_init() after failed memory allocation
xfs: fix broken log reservation debugging
clocksource/drivers/timer-ti-dm: Change to new style declaration
ASoC: core: lock client_mutex while removing link components
ASoC: simple-card: Restore original configuration of DAI format
{nl,mac}80211: allow 4addr AP operation on crypto controlled devices
mac80211_hwsim: mark expected switch fall-through
mac80211: fix rate reporting inside cfg80211_calculate_bitrate_he()
mac80211: remove set but not used variable 'old'
mac80211: handle deauthentication/disassociation from TDLS peer
gpio: fix gpio-adp5588 build errors
pinctrl: stmfx: Fix compile issue when CONFIG_OF_GPIO is not defined
staging: kpc2000: Add dependency on MFD_CORE to kconfig symbol 'KPC2000'
perf/ring-buffer: Use regular variables for nesting
perf/ring-buffer: Always use {READ,WRITE}_ONCE() for rb->user_page data
perf/ring_buffer: Add ordering to rb->nest increment
perf/ring_buffer: Fix exposing a temporarily decreased data_head
x86/CPU/AMD: Don't force the CPB cap when running under a hypervisor
x86/boot: Provide KASAN compatible aliases for string routines
ALSA: hda/realtek - Enable micmute LED for Huawei laptops
Input: uinput - add compat ioctl number translation for UI_*_FF_UPLOAD
Input: silead - add MSSL0017 to acpi_device_id
cxgb4: offload VLAN flows regardless of VLAN ethtype
hsr: fix don't prune the master node from the node_db
net: mvpp2: cls: Fix leaked ethtool_rx_flow_rule
docs: fix multiple doc build warnings in enumeration.rst
lib/list_sort: fix kerneldoc build error
docs: fix numaperf.rst and add it to the doc tree
doc: Cope with the deprecation of AutoReporter
doc: Cope with Sphinx logging deprecations
bpf: sockmap, restore sk_write_space when psock gets dropped
selftests: bpf: add zero extend checks for ALU32 and/or/xor
bpf, riscv: clear target register high 32-bits for and/or/xor on ALU32
spi: abort spi_sync if failed to prepare_transfer_hardware
ALSA: hda/realtek - Set default power save node to 0
ipv4/igmp: fix build error if !CONFIG_IP_MULTICAST
powerpc/kexec: Fix loading of kernel + initramfs with kexec_file_load()
MIPS: TXx9: Fix boot crash in free_initmem()
MIPS: remove a space after -I to cope with header search paths for VDSO
MIPS: mark ginvt() as __always_inline
ipv4/igmp: fix another memory leak in igmpv3_del_delrec()
bnxt_en: Device serial number is supported only for PFs.
bnxt_en: Reduce memory usage when running in kdump kernel.
bnxt_en: Fix possible BUG() condition when calling pci_disable_msix().
bnxt_en: Fix aggregation buffer leak under OOM condition.
ipv6: Fix redirect with VRF
net: stmmac: fix reset gpio free missing
mISDN: make sure device name is NUL terminated
net: macb: save/restore the remaining registers and features
media: dvb: warning about dvb frequency limits produces too much noise
net/tls: don't ignore netdev notifications if no TLS features
net/tls: fix state removal with feature flags off
net/tls: avoid NULL-deref on resync during device removal
Documentation: add TLS offload documentation
Documentation: tls: RSTify the ktls documentation
Documentation: net: move device drivers docs to a submenu
mISDN: Fix indenting in dsp_cmx.c
ocelot: Dont allocate another multicast list, use __dev_mc_sync
Validate required parameters in inet6_validate_link_af
xhci: Use %zu for printing size_t type
xhci: Convert xhci_handshake() to use readl_poll_timeout_atomic()
xhci: Fix immediate data transfer if buffer is already DMA mapped
usb: xhci: avoid null pointer deref when bos field is NULL
usb: xhci: Fix a potential null pointer dereference in xhci_debugfs_create_endpoint()
xhci: update bounce buffer with correct sg num
media: usb: siano: Fix false-positive "uninitialized variable" warning
spi: spi-fsl-spi: call spi_finalize_current_message() at the end
ALSA: hda/realtek - Check headset type by unplug and resume
powerpc/perf: Fix MMCRA corruption by bhrb_filter
powerpc/powernv: Return for invalid IMC domain
HID: logitech-hidpp: Add support for the S510 remote control
HID: multitouch: handle faulty Elo touch device
selftests: netfilter: add flowtable test script
netfilter: nft_flow_offload: IPCB is only valid for ipv4 family
netfilter: nft_flow_offload: don't offload when sequence numbers need adjustment
netfilter: nft_flow_offload: set liberal tracking mode for tcp
netfilter: nf_flow_table: ignore DF bit setting
ASoC: Intel: sof-rt5682: fix AMP quirk support
ASoC: Intel: sof-rt5682: fix for codec button mapping
clk: ti: clkctrl: Fix clkdm_clk handling
clk: imx: imx8mm: fix int pll clk gate
clk: sifive: restrict Kconfig scope for the FU540 PRCI driver
RDMA/hns: Fix PD memory leak for internal allocation
netfilter: nat: fix udp checksum corruption
selftests: netfilter: missing error check when setting up veth interface
RDMA/srp: Rename SRP sysfs name after IB device rename trigger
ipvs: Fix use-after-free in ip_vs_in
ARC: [plat-hsdk]: Add missing FIFO size entry in GMAC node
ARC: [plat-hsdk]: Add missing multicast filter bins number to GMAC node
samples, bpf: suppress compiler warning
samples, bpf: fix to change the buffer size for read()
bpf: Check sk_fullsock() before returning from bpf_sk_lookup()
bpf: fix out-of-bounds read in __bpf_skc_lookup
Documentation/networking: fix af_xdp.rst Sphinx warnings
netfilter: nft_fib: Fix existence check support
netfilter: nf_queue: fix reinject verdict handling
dmaengine: sprd: Add interrupt support for 2-stage transfer
dmaengine: sprd: Fix the right place to configure 2-stage transfer
dmaengine: sprd: Fix block length overflow
dmaengine: sprd: Fix the incorrect start for 2-stage destination channels
dmaengine: sprd: Add validation of current descriptor in irq handler
dmaengine: sprd: Fix the possible crash when getting descriptor status
tty: max310x: Fix external crystal register setup
serial: sh-sci: disable DMA for uart_console
serial: imx: remove log spamming error message
tty: serial: msm_serial: Fix XON/XOFF
USB: serial: option: add Telit 0x1260 and 0x1261 compositions
USB: serial: pl2303: add Allied Telesis VT-Kit3
USB: serial: option: add support for Simcom SIM7500/SIM7600 RNDIS mode
dmaengine: tegra210-adma: Fix spelling
dmaengine: tegra210-adma: Fix channel FIFO configuration
dmaengine: tegra210-adma: Fix crash during probe
dmaengine: mediatek-cqdma: sleeping in atomic context
dmaengine: dw-axi-dmac: fix null dereference when pointer first is null
perf/x86/intel/ds: Fix EVENT vs. UEVENT PEBS constraints
USB: rio500: update Documentation
USB: rio500: simplify locking
USB: rio500: fix memory leak in close after disconnect
USB: rio500: refuse more than one device at a time
usbip: usbip_host: fix BUG: sleeping function called from invalid context
USB: sisusbvga: fix oops in error path of sisusb_probe
USB: Add LPM quirk for Surface Dock GigE adapter
media: usb: siano: Fix general protection fault in smsusb
usb: mtu3: fix up undefined reference to usb_debug_root
USB: Fix slab-out-of-bounds write in usb_get_bos_descriptor
Input: elantech - enable middle button support on 2 ThinkPads
dmaengine: fsl-qdma: Add improvement
dmaengine: jz4780: Fix transfers being ACKed too soon
gcc-plugins: Fix build failures under Darwin host
MAINTAINERS: Update Stefan Wahren email address
netfilter: nf_tables: fix oops during rule dump
ARC: mm: SIGSEGV userspace trying to access kernel virtual memory
ARC: fix build warnings
ARM: dts: bcm: Add missing device_type = "memory" property
soc: bcm: brcmstb: biuctrl: Register writes require a barrier
soc: brcmstb: Fix error path for unsupported CPUs
ARM: dts: dra71x: Disable usb4_tm target module
ARM: dts: dra71x: Disable rtc target module
ARM: dts: dra76x: Disable usb4_tm target module
ARM: dts: dra76x: Disable rtc target module
ASoC: simple-card: Fix configuration of DAI format
ASoC: Intel: soc-acpi: Fix machine selection order
ASoC: rt5677-spi: Handle over reading when flipping bytes
ASoC: soc-dpm: fixup DAI active unbalance
pinctrl: intel: Clear interrupt status in mask/unmask callback
pinctrl: intel: Use GENMASK() consistently
parisc: Allow building 64-bit kernel without -mlong-calls compiler option
parisc: Kconfig: remove ARCH_DISCARD_MEMBLOCK
staging: wilc1000: Fix some double unlock bugs in wilc_wlan_cleanup()
staging: vc04_services: prevent integer overflow in create_pagelist()
Staging: vc04_services: Fix a couple error codes
staging: wlan-ng: fix adapter initialization failure
staging: kpc2000: double unlock in error handling in kpc_dma_transfer()
staging: kpc2000: Fix build error without CONFIG_UIO
staging: kpc2000: fix build error on xtensa
staging: erofs: set sb->s_root to NULL when failing from __getname()
ARM: imx: cpuidle-imx6sx: Restrict the SW2ISO increase to i.MX6SX
firmware: imx: SCU irq should ONLY be enabled after SCU IPC is ready
arm64: imx: Fix build error without CONFIG_SOC_BUS
ima: fix wrong signed policy requirement when not appraising
x86/ima: Check EFI_RUNTIME_SERVICES before using
stacktrace: Unbreak stack_trace_save_tsk_reliable()
HID: wacom: Sync INTUOSP2_BT touch state after each frame if necessary
HID: wacom: Correct button numbering 2nd-gen Intuos Pro over Bluetooth
HID: wacom: Send BTN_TOUCH in response to INTUOSP2_BT eraser contact
HID: wacom: Don't report anything prior to the tool entering range
HID: wacom: Don't set tool type until we're in range
ASoC: cs42xx8: Add regcache mask dirty
regulator: tps6507x: Fix boot regression due to testing wrong init_data pointer
ASoC: fsl_asrc: Fix the issue about unsupported rate
spi: bitbang: Fix NULL pointer dereference in spi_unregister_master
Input: elan_i2c - increment wakeup count if wake source
wireless: Skip directory when generating certificates
ASoC: ak4458: rstn_control - return a non-zero on error only
ASoC: soc-pcm: BE dai needs prepare when pause release after resume
ASoC: ak4458: add return value for ak4458_probe
ASoC : cs4265 : readable register too low
ASoC: SOF: fix error in verbose ipc command parsing
ASoC: SOF: fix race in FW boot timeout handling
ASoC: SOF: nocodec: fix undefined reference
iio: adc: ti-ads8688: fix timestamp is not updated in buffer
iio: dac: ds4422/ds4424 fix chip verification
HID: rmi: Use SET_REPORT request on control endpoint for Acer Switch 3 and 5
HID: logitech-hidpp: add support for the MX5500 keyboard
HID: logitech-dj: add support for the Logitech MX5500's Bluetooth Mini-Receiver
HID: i2c-hid: add iBall Aer3 to descriptor override
spi: Fix Raspberry Pi breakage
ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values
ARM: dts: am57xx-idk: Remove support for voltage switching for SD card
bus: ti-sysc: Handle devices with no control registers
ARM: dts: Configure osc clock for d_can on am335x
iio: imu: mpu6050: Fix FIFO layout for ICM20602
lkdtm/bugs: Adjust recursion test to avoid elision
lkdtm/usercopy: Moves the KERNEL_DS test to non-canonical
iio: adc: ads124: avoid buffer overflow
iio: adc: modify NPCM ADC read reference voltage
Change-Id: I98c823993370027391cc21dfb239c3049f025136
Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org>
2925 lines
70 KiB
C
2925 lines
70 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* cp1emu.c: a MIPS coprocessor 1 (FPU) instruction emulator
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*
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* MIPS floating point support
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* Copyright (C) 1994-2000 Algorithmics Ltd.
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*
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* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
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* Copyright (C) 2000 MIPS Technologies, Inc.
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*
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* A complete emulator for MIPS coprocessor 1 instructions. This is
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* required for #float(switch) or #float(trap), where it catches all
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* COP1 instructions via the "CoProcessor Unusable" exception.
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*
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* More surprisingly it is also required for #float(ieee), to help out
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* the hardware FPU at the boundaries of the IEEE-754 representation
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* (denormalised values, infinities, underflow, etc). It is made
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* quite nasty because emulation of some non-COP1 instructions is
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* required, e.g. in branch delay slots.
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*
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* Note if you know that you won't have an FPU, then you'll get much
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* better performance by compiling with -msoft-float!
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*/
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#include <linux/sched.h>
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#include <linux/debugfs.h>
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#include <linux/percpu-defs.h>
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#include <linux/perf_event.h>
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#include <asm/branch.h>
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#include <asm/inst.h>
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#include <asm/ptrace.h>
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#include <asm/signal.h>
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#include <linux/uaccess.h>
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#include <asm/cpu-info.h>
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#include <asm/processor.h>
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#include <asm/fpu_emulator.h>
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#include <asm/fpu.h>
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#include <asm/mips-r2-to-r6-emul.h>
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#include "ieee754.h"
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/* Function which emulates a floating point instruction. */
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static int fpu_emu(struct pt_regs *, struct mips_fpu_struct *,
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mips_instruction);
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static int fpux_emu(struct pt_regs *,
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struct mips_fpu_struct *, mips_instruction, void __user **);
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/* Control registers */
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#define FPCREG_RID 0 /* $0 = revision id */
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#define FPCREG_FCCR 25 /* $25 = fccr */
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#define FPCREG_FEXR 26 /* $26 = fexr */
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#define FPCREG_FENR 28 /* $28 = fenr */
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#define FPCREG_CSR 31 /* $31 = csr */
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/* convert condition code register number to csr bit */
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const unsigned int fpucondbit[8] = {
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FPU_CSR_COND,
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FPU_CSR_COND1,
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FPU_CSR_COND2,
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FPU_CSR_COND3,
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FPU_CSR_COND4,
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FPU_CSR_COND5,
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FPU_CSR_COND6,
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FPU_CSR_COND7
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};
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/* (microMIPS) Convert certain microMIPS instructions to MIPS32 format. */
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static const int sd_format[] = {16, 17, 0, 0, 0, 0, 0, 0};
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static const int sdps_format[] = {16, 17, 22, 0, 0, 0, 0, 0};
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static const int dwl_format[] = {17, 20, 21, 0, 0, 0, 0, 0};
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static const int swl_format[] = {16, 20, 21, 0, 0, 0, 0, 0};
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/*
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* This functions translates a 32-bit microMIPS instruction
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* into a 32-bit MIPS32 instruction. Returns 0 on success
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* and SIGILL otherwise.
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*/
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static int microMIPS32_to_MIPS32(union mips_instruction *insn_ptr)
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{
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union mips_instruction insn = *insn_ptr;
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union mips_instruction mips32_insn = insn;
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int func, fmt, op;
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switch (insn.mm_i_format.opcode) {
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case mm_ldc132_op:
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mips32_insn.mm_i_format.opcode = ldc1_op;
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mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
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mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
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break;
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case mm_lwc132_op:
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mips32_insn.mm_i_format.opcode = lwc1_op;
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mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
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mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
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break;
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case mm_sdc132_op:
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mips32_insn.mm_i_format.opcode = sdc1_op;
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mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
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mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
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break;
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case mm_swc132_op:
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mips32_insn.mm_i_format.opcode = swc1_op;
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mips32_insn.mm_i_format.rt = insn.mm_i_format.rs;
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mips32_insn.mm_i_format.rs = insn.mm_i_format.rt;
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break;
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case mm_pool32i_op:
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/* NOTE: offset is << by 1 if in microMIPS mode. */
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if ((insn.mm_i_format.rt == mm_bc1f_op) ||
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(insn.mm_i_format.rt == mm_bc1t_op)) {
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mips32_insn.fb_format.opcode = cop1_op;
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mips32_insn.fb_format.bc = bc_op;
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mips32_insn.fb_format.flag =
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(insn.mm_i_format.rt == mm_bc1t_op) ? 1 : 0;
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} else
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return SIGILL;
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break;
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case mm_pool32f_op:
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switch (insn.mm_fp0_format.func) {
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case mm_32f_01_op:
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case mm_32f_11_op:
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case mm_32f_02_op:
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case mm_32f_12_op:
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case mm_32f_41_op:
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case mm_32f_51_op:
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case mm_32f_42_op:
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case mm_32f_52_op:
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op = insn.mm_fp0_format.func;
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if (op == mm_32f_01_op)
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func = madd_s_op;
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else if (op == mm_32f_11_op)
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func = madd_d_op;
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else if (op == mm_32f_02_op)
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func = nmadd_s_op;
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else if (op == mm_32f_12_op)
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func = nmadd_d_op;
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else if (op == mm_32f_41_op)
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func = msub_s_op;
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else if (op == mm_32f_51_op)
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func = msub_d_op;
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else if (op == mm_32f_42_op)
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func = nmsub_s_op;
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else
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func = nmsub_d_op;
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mips32_insn.fp6_format.opcode = cop1x_op;
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mips32_insn.fp6_format.fr = insn.mm_fp6_format.fr;
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mips32_insn.fp6_format.ft = insn.mm_fp6_format.ft;
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mips32_insn.fp6_format.fs = insn.mm_fp6_format.fs;
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mips32_insn.fp6_format.fd = insn.mm_fp6_format.fd;
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mips32_insn.fp6_format.func = func;
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break;
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case mm_32f_10_op:
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func = -1; /* Invalid */
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op = insn.mm_fp5_format.op & 0x7;
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if (op == mm_ldxc1_op)
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func = ldxc1_op;
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else if (op == mm_sdxc1_op)
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func = sdxc1_op;
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else if (op == mm_lwxc1_op)
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func = lwxc1_op;
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else if (op == mm_swxc1_op)
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func = swxc1_op;
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if (func != -1) {
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mips32_insn.r_format.opcode = cop1x_op;
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mips32_insn.r_format.rs =
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insn.mm_fp5_format.base;
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mips32_insn.r_format.rt =
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insn.mm_fp5_format.index;
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mips32_insn.r_format.rd = 0;
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mips32_insn.r_format.re = insn.mm_fp5_format.fd;
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mips32_insn.r_format.func = func;
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} else
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return SIGILL;
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break;
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case mm_32f_40_op:
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op = -1; /* Invalid */
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if (insn.mm_fp2_format.op == mm_fmovt_op)
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op = 1;
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else if (insn.mm_fp2_format.op == mm_fmovf_op)
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op = 0;
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if (op != -1) {
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sdps_format[insn.mm_fp2_format.fmt];
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mips32_insn.fp0_format.ft =
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(insn.mm_fp2_format.cc<<2) + op;
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mips32_insn.fp0_format.fs =
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insn.mm_fp2_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp2_format.fd;
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mips32_insn.fp0_format.func = fmovc_op;
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} else
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return SIGILL;
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break;
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case mm_32f_60_op:
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func = -1; /* Invalid */
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if (insn.mm_fp0_format.op == mm_fadd_op)
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func = fadd_op;
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else if (insn.mm_fp0_format.op == mm_fsub_op)
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func = fsub_op;
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else if (insn.mm_fp0_format.op == mm_fmul_op)
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func = fmul_op;
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else if (insn.mm_fp0_format.op == mm_fdiv_op)
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func = fdiv_op;
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if (func != -1) {
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sdps_format[insn.mm_fp0_format.fmt];
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mips32_insn.fp0_format.ft =
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insn.mm_fp0_format.ft;
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mips32_insn.fp0_format.fs =
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insn.mm_fp0_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp0_format.fd;
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mips32_insn.fp0_format.func = func;
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} else
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return SIGILL;
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break;
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case mm_32f_70_op:
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func = -1; /* Invalid */
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if (insn.mm_fp0_format.op == mm_fmovn_op)
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func = fmovn_op;
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else if (insn.mm_fp0_format.op == mm_fmovz_op)
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func = fmovz_op;
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if (func != -1) {
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sdps_format[insn.mm_fp0_format.fmt];
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mips32_insn.fp0_format.ft =
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insn.mm_fp0_format.ft;
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mips32_insn.fp0_format.fs =
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insn.mm_fp0_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp0_format.fd;
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mips32_insn.fp0_format.func = func;
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} else
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return SIGILL;
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break;
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case mm_32f_73_op: /* POOL32FXF */
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switch (insn.mm_fp1_format.op) {
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case mm_movf0_op:
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case mm_movf1_op:
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case mm_movt0_op:
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case mm_movt1_op:
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if ((insn.mm_fp1_format.op & 0x7f) ==
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mm_movf0_op)
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op = 0;
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else
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op = 1;
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mips32_insn.r_format.opcode = spec_op;
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mips32_insn.r_format.rs = insn.mm_fp4_format.fs;
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mips32_insn.r_format.rt =
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(insn.mm_fp4_format.cc << 2) + op;
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mips32_insn.r_format.rd = insn.mm_fp4_format.rt;
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mips32_insn.r_format.re = 0;
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mips32_insn.r_format.func = movc_op;
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break;
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case mm_fcvtd0_op:
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case mm_fcvtd1_op:
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case mm_fcvts0_op:
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case mm_fcvts1_op:
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if ((insn.mm_fp1_format.op & 0x7f) ==
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mm_fcvtd0_op) {
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func = fcvtd_op;
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fmt = swl_format[insn.mm_fp3_format.fmt];
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} else {
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func = fcvts_op;
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fmt = dwl_format[insn.mm_fp3_format.fmt];
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}
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt = fmt;
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mips32_insn.fp0_format.ft = 0;
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mips32_insn.fp0_format.fs =
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insn.mm_fp3_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp3_format.rt;
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mips32_insn.fp0_format.func = func;
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break;
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case mm_fmov0_op:
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case mm_fmov1_op:
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case mm_fabs0_op:
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case mm_fabs1_op:
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case mm_fneg0_op:
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case mm_fneg1_op:
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if ((insn.mm_fp1_format.op & 0x7f) ==
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mm_fmov0_op)
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func = fmov_op;
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else if ((insn.mm_fp1_format.op & 0x7f) ==
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mm_fabs0_op)
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func = fabs_op;
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else
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func = fneg_op;
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mips32_insn.fp0_format.opcode = cop1_op;
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mips32_insn.fp0_format.fmt =
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sdps_format[insn.mm_fp3_format.fmt];
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mips32_insn.fp0_format.ft = 0;
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mips32_insn.fp0_format.fs =
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insn.mm_fp3_format.fs;
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mips32_insn.fp0_format.fd =
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insn.mm_fp3_format.rt;
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mips32_insn.fp0_format.func = func;
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break;
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case mm_ffloorl_op:
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case mm_ffloorw_op:
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case mm_fceill_op:
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case mm_fceilw_op:
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case mm_ftruncl_op:
|
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case mm_ftruncw_op:
|
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case mm_froundl_op:
|
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case mm_froundw_op:
|
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case mm_fcvtl_op:
|
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case mm_fcvtw_op:
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if (insn.mm_fp1_format.op == mm_ffloorl_op)
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func = ffloorl_op;
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else if (insn.mm_fp1_format.op == mm_ffloorw_op)
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func = ffloor_op;
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else if (insn.mm_fp1_format.op == mm_fceill_op)
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func = fceill_op;
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else if (insn.mm_fp1_format.op == mm_fceilw_op)
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func = fceil_op;
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else if (insn.mm_fp1_format.op == mm_ftruncl_op)
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func = ftruncl_op;
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else if (insn.mm_fp1_format.op == mm_ftruncw_op)
|
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func = ftrunc_op;
|
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else if (insn.mm_fp1_format.op == mm_froundl_op)
|
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func = froundl_op;
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else if (insn.mm_fp1_format.op == mm_froundw_op)
|
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func = fround_op;
|
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else if (insn.mm_fp1_format.op == mm_fcvtl_op)
|
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func = fcvtl_op;
|
|
else
|
|
func = fcvtw_op;
|
|
mips32_insn.fp0_format.opcode = cop1_op;
|
|
mips32_insn.fp0_format.fmt =
|
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sd_format[insn.mm_fp1_format.fmt];
|
|
mips32_insn.fp0_format.ft = 0;
|
|
mips32_insn.fp0_format.fs =
|
|
insn.mm_fp1_format.fs;
|
|
mips32_insn.fp0_format.fd =
|
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insn.mm_fp1_format.rt;
|
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mips32_insn.fp0_format.func = func;
|
|
break;
|
|
case mm_frsqrt_op:
|
|
case mm_fsqrt_op:
|
|
case mm_frecip_op:
|
|
if (insn.mm_fp1_format.op == mm_frsqrt_op)
|
|
func = frsqrt_op;
|
|
else if (insn.mm_fp1_format.op == mm_fsqrt_op)
|
|
func = fsqrt_op;
|
|
else
|
|
func = frecip_op;
|
|
mips32_insn.fp0_format.opcode = cop1_op;
|
|
mips32_insn.fp0_format.fmt =
|
|
sdps_format[insn.mm_fp1_format.fmt];
|
|
mips32_insn.fp0_format.ft = 0;
|
|
mips32_insn.fp0_format.fs =
|
|
insn.mm_fp1_format.fs;
|
|
mips32_insn.fp0_format.fd =
|
|
insn.mm_fp1_format.rt;
|
|
mips32_insn.fp0_format.func = func;
|
|
break;
|
|
case mm_mfc1_op:
|
|
case mm_mtc1_op:
|
|
case mm_cfc1_op:
|
|
case mm_ctc1_op:
|
|
case mm_mfhc1_op:
|
|
case mm_mthc1_op:
|
|
if (insn.mm_fp1_format.op == mm_mfc1_op)
|
|
op = mfc_op;
|
|
else if (insn.mm_fp1_format.op == mm_mtc1_op)
|
|
op = mtc_op;
|
|
else if (insn.mm_fp1_format.op == mm_cfc1_op)
|
|
op = cfc_op;
|
|
else if (insn.mm_fp1_format.op == mm_ctc1_op)
|
|
op = ctc_op;
|
|
else if (insn.mm_fp1_format.op == mm_mfhc1_op)
|
|
op = mfhc_op;
|
|
else
|
|
op = mthc_op;
|
|
mips32_insn.fp1_format.opcode = cop1_op;
|
|
mips32_insn.fp1_format.op = op;
|
|
mips32_insn.fp1_format.rt =
|
|
insn.mm_fp1_format.rt;
|
|
mips32_insn.fp1_format.fs =
|
|
insn.mm_fp1_format.fs;
|
|
mips32_insn.fp1_format.fd = 0;
|
|
mips32_insn.fp1_format.func = 0;
|
|
break;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
case mm_32f_74_op: /* c.cond.fmt */
|
|
mips32_insn.fp0_format.opcode = cop1_op;
|
|
mips32_insn.fp0_format.fmt =
|
|
sdps_format[insn.mm_fp4_format.fmt];
|
|
mips32_insn.fp0_format.ft = insn.mm_fp4_format.rt;
|
|
mips32_insn.fp0_format.fs = insn.mm_fp4_format.fs;
|
|
mips32_insn.fp0_format.fd = insn.mm_fp4_format.cc << 2;
|
|
mips32_insn.fp0_format.func =
|
|
insn.mm_fp4_format.cond | MM_MIPS32_COND_FC;
|
|
break;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
*insn_ptr = mips32_insn;
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Redundant with logic already in kernel/branch.c,
|
|
* embedded in compute_return_epc. At some point,
|
|
* a single subroutine should be used across both
|
|
* modules.
|
|
*/
|
|
int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
|
|
unsigned long *contpc)
|
|
{
|
|
union mips_instruction insn = (union mips_instruction)dec_insn.insn;
|
|
unsigned int fcr31;
|
|
unsigned int bit = 0;
|
|
unsigned int bit0;
|
|
union fpureg *fpr;
|
|
|
|
switch (insn.i_format.opcode) {
|
|
case spec_op:
|
|
switch (insn.r_format.func) {
|
|
case jalr_op:
|
|
if (insn.r_format.rd != 0) {
|
|
regs->regs[insn.r_format.rd] =
|
|
regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
}
|
|
/* fall through */
|
|
case jr_op:
|
|
/* For R6, JR already emulated in jalr_op */
|
|
if (NO_R6EMU && insn.r_format.func == jr_op)
|
|
break;
|
|
*contpc = regs->regs[insn.r_format.rs];
|
|
return 1;
|
|
}
|
|
break;
|
|
case bcond_op:
|
|
switch (insn.i_format.rt) {
|
|
case bltzal_op:
|
|
case bltzall_op:
|
|
if (NO_R6EMU && (insn.i_format.rs ||
|
|
insn.i_format.rt == bltzall_op))
|
|
break;
|
|
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
/* fall through */
|
|
case bltzl_op:
|
|
if (NO_R6EMU)
|
|
break;
|
|
/* fall through */
|
|
case bltz_op:
|
|
if ((long)regs->regs[insn.i_format.rs] < 0)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case bgezal_op:
|
|
case bgezall_op:
|
|
if (NO_R6EMU && (insn.i_format.rs ||
|
|
insn.i_format.rt == bgezall_op))
|
|
break;
|
|
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
/* fall through */
|
|
case bgezl_op:
|
|
if (NO_R6EMU)
|
|
break;
|
|
/* fall through */
|
|
case bgez_op:
|
|
if ((long)regs->regs[insn.i_format.rs] >= 0)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
}
|
|
break;
|
|
case jalx_op:
|
|
set_isa16_mode(bit);
|
|
/* fall through */
|
|
case jal_op:
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
/* fall through */
|
|
case j_op:
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc;
|
|
*contpc >>= 28;
|
|
*contpc <<= 28;
|
|
*contpc |= (insn.j_format.target << 2);
|
|
/* Set microMIPS mode bit: XOR for jalx. */
|
|
*contpc ^= bit;
|
|
return 1;
|
|
case beql_op:
|
|
if (NO_R6EMU)
|
|
break;
|
|
/* fall through */
|
|
case beq_op:
|
|
if (regs->regs[insn.i_format.rs] ==
|
|
regs->regs[insn.i_format.rt])
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case bnel_op:
|
|
if (NO_R6EMU)
|
|
break;
|
|
/* fall through */
|
|
case bne_op:
|
|
if (regs->regs[insn.i_format.rs] !=
|
|
regs->regs[insn.i_format.rt])
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case blezl_op:
|
|
if (!insn.i_format.rt && NO_R6EMU)
|
|
break;
|
|
/* fall through */
|
|
case blez_op:
|
|
|
|
/*
|
|
* Compact branches for R6 for the
|
|
* blez and blezl opcodes.
|
|
* BLEZ | rs = 0 | rt != 0 == BLEZALC
|
|
* BLEZ | rs = rt != 0 == BGEZALC
|
|
* BLEZ | rs != 0 | rt != 0 == BGEUC
|
|
* BLEZL | rs = 0 | rt != 0 == BLEZC
|
|
* BLEZL | rs = rt != 0 == BGEZC
|
|
* BLEZL | rs != 0 | rt != 0 == BGEC
|
|
*
|
|
* For real BLEZ{,L}, rt is always 0.
|
|
*/
|
|
if (cpu_has_mips_r6 && insn.i_format.rt) {
|
|
if ((insn.i_format.opcode == blez_op) &&
|
|
((!insn.i_format.rs && insn.i_format.rt) ||
|
|
(insn.i_format.rs == insn.i_format.rt)))
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
}
|
|
if ((long)regs->regs[insn.i_format.rs] <= 0)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case bgtzl_op:
|
|
if (!insn.i_format.rt && NO_R6EMU)
|
|
break;
|
|
/* fall through */
|
|
case bgtz_op:
|
|
/*
|
|
* Compact branches for R6 for the
|
|
* bgtz and bgtzl opcodes.
|
|
* BGTZ | rs = 0 | rt != 0 == BGTZALC
|
|
* BGTZ | rs = rt != 0 == BLTZALC
|
|
* BGTZ | rs != 0 | rt != 0 == BLTUC
|
|
* BGTZL | rs = 0 | rt != 0 == BGTZC
|
|
* BGTZL | rs = rt != 0 == BLTZC
|
|
* BGTZL | rs != 0 | rt != 0 == BLTC
|
|
*
|
|
* *ZALC varint for BGTZ &&& rt != 0
|
|
* For real GTZ{,L}, rt is always 0.
|
|
*/
|
|
if (cpu_has_mips_r6 && insn.i_format.rt) {
|
|
if ((insn.i_format.opcode == blez_op) &&
|
|
((!insn.i_format.rs && insn.i_format.rt) ||
|
|
(insn.i_format.rs == insn.i_format.rt)))
|
|
regs->regs[31] = regs->cp0_epc +
|
|
dec_insn.pc_inc;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
}
|
|
|
|
if ((long)regs->regs[insn.i_format.rs] > 0)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case pop10_op:
|
|
case pop30_op:
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
if (insn.i_format.rt && !insn.i_format.rs)
|
|
regs->regs[31] = regs->cp0_epc + 4;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
#ifdef CONFIG_CPU_CAVIUM_OCTEON
|
|
case lwc2_op: /* This is bbit0 on Octeon */
|
|
if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt)) == 0)
|
|
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc + 8;
|
|
return 1;
|
|
case ldc2_op: /* This is bbit032 on Octeon */
|
|
if ((regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32))) == 0)
|
|
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc + 8;
|
|
return 1;
|
|
case swc2_op: /* This is bbit1 on Octeon */
|
|
if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
|
|
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc + 8;
|
|
return 1;
|
|
case sdc2_op: /* This is bbit132 on Octeon */
|
|
if (regs->regs[insn.i_format.rs] & (1ull<<(insn.i_format.rt + 32)))
|
|
*contpc = regs->cp0_epc + 4 + (insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc + 8;
|
|
return 1;
|
|
#else
|
|
case bc6_op:
|
|
/*
|
|
* Only valid for MIPS R6 but we can still end up
|
|
* here from a broken userland so just tell emulator
|
|
* this is not a branch and let it break later on.
|
|
*/
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
case balc6_op:
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
regs->regs[31] = regs->cp0_epc + 4;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
case pop66_op:
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
case pop76_op:
|
|
if (!cpu_has_mips_r6)
|
|
break;
|
|
if (!insn.i_format.rs)
|
|
regs->regs[31] = regs->cp0_epc + 4;
|
|
*contpc = regs->cp0_epc + dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
#endif
|
|
case cop0_op:
|
|
case cop1_op:
|
|
/* Need to check for R6 bc1nez and bc1eqz branches */
|
|
if (cpu_has_mips_r6 &&
|
|
((insn.i_format.rs == bc1eqz_op) ||
|
|
(insn.i_format.rs == bc1nez_op))) {
|
|
bit = 0;
|
|
fpr = ¤t->thread.fpu.fpr[insn.i_format.rt];
|
|
bit0 = get_fpr32(fpr, 0) & 0x1;
|
|
switch (insn.i_format.rs) {
|
|
case bc1eqz_op:
|
|
bit = bit0 == 0;
|
|
break;
|
|
case bc1nez_op:
|
|
bit = bit0 != 0;
|
|
break;
|
|
}
|
|
if (bit)
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
|
|
return 1;
|
|
}
|
|
/* R2/R6 compatible cop1 instruction */
|
|
/* fall through */
|
|
case cop2_op:
|
|
case cop1x_op:
|
|
if (insn.i_format.rs == bc_op) {
|
|
preempt_disable();
|
|
if (is_fpu_owner())
|
|
fcr31 = read_32bit_cp1_register(CP1_STATUS);
|
|
else
|
|
fcr31 = current->thread.fpu.fcr31;
|
|
preempt_enable();
|
|
|
|
bit = (insn.i_format.rt >> 2);
|
|
bit += (bit != 0);
|
|
bit += 23;
|
|
switch (insn.i_format.rt & 3) {
|
|
case 0: /* bc1f */
|
|
case 2: /* bc1fl */
|
|
if (~fcr31 & (1 << bit))
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
case 1: /* bc1t */
|
|
case 3: /* bc1tl */
|
|
if (fcr31 & (1 << bit))
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
(insn.i_format.simmediate << 2);
|
|
else
|
|
*contpc = regs->cp0_epc +
|
|
dec_insn.pc_inc +
|
|
dec_insn.next_pc_inc;
|
|
return 1;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* In the Linux kernel, we support selection of FPR format on the
|
|
* basis of the Status.FR bit. If an FPU is not present, the FR bit
|
|
* is hardwired to zero, which would imply a 32-bit FPU even for
|
|
* 64-bit CPUs so we rather look at TIF_32BIT_FPREGS.
|
|
* FPU emu is slow and bulky and optimizing this function offers fairly
|
|
* sizeable benefits so we try to be clever and make this function return
|
|
* a constant whenever possible, that is on 64-bit kernels without O32
|
|
* compatibility enabled and on 32-bit without 64-bit FPU support.
|
|
*/
|
|
static inline int cop1_64bit(struct pt_regs *xcp)
|
|
{
|
|
if (IS_ENABLED(CONFIG_64BIT) && !IS_ENABLED(CONFIG_MIPS32_O32))
|
|
return 1;
|
|
else if (IS_ENABLED(CONFIG_32BIT) &&
|
|
!IS_ENABLED(CONFIG_MIPS_O32_FP64_SUPPORT))
|
|
return 0;
|
|
|
|
return !test_thread_flag(TIF_32BIT_FPREGS);
|
|
}
|
|
|
|
static inline bool hybrid_fprs(void)
|
|
{
|
|
return test_thread_flag(TIF_HYBRID_FPREGS);
|
|
}
|
|
|
|
#define SIFROMREG(si, x) \
|
|
do { \
|
|
if (cop1_64bit(xcp) && !hybrid_fprs()) \
|
|
(si) = (int)get_fpr32(&ctx->fpr[x], 0); \
|
|
else \
|
|
(si) = (int)get_fpr32(&ctx->fpr[(x) & ~1], (x) & 1); \
|
|
} while (0)
|
|
|
|
#define SITOREG(si, x) \
|
|
do { \
|
|
if (cop1_64bit(xcp) && !hybrid_fprs()) { \
|
|
unsigned int i; \
|
|
set_fpr32(&ctx->fpr[x], 0, si); \
|
|
for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
|
|
set_fpr32(&ctx->fpr[x], i, 0); \
|
|
} else { \
|
|
set_fpr32(&ctx->fpr[(x) & ~1], (x) & 1, si); \
|
|
} \
|
|
} while (0)
|
|
|
|
#define SIFROMHREG(si, x) ((si) = (int)get_fpr32(&ctx->fpr[x], 1))
|
|
|
|
#define SITOHREG(si, x) \
|
|
do { \
|
|
unsigned int i; \
|
|
set_fpr32(&ctx->fpr[x], 1, si); \
|
|
for (i = 2; i < ARRAY_SIZE(ctx->fpr[x].val32); i++) \
|
|
set_fpr32(&ctx->fpr[x], i, 0); \
|
|
} while (0)
|
|
|
|
#define DIFROMREG(di, x) \
|
|
((di) = get_fpr64(&ctx->fpr[(x) & ~(cop1_64bit(xcp) ^ 1)], 0))
|
|
|
|
#define DITOREG(di, x) \
|
|
do { \
|
|
unsigned int fpr, i; \
|
|
fpr = (x) & ~(cop1_64bit(xcp) ^ 1); \
|
|
set_fpr64(&ctx->fpr[fpr], 0, di); \
|
|
for (i = 1; i < ARRAY_SIZE(ctx->fpr[x].val64); i++) \
|
|
set_fpr64(&ctx->fpr[fpr], i, 0); \
|
|
} while (0)
|
|
|
|
#define SPFROMREG(sp, x) SIFROMREG((sp).bits, x)
|
|
#define SPTOREG(sp, x) SITOREG((sp).bits, x)
|
|
#define DPFROMREG(dp, x) DIFROMREG((dp).bits, x)
|
|
#define DPTOREG(dp, x) DITOREG((dp).bits, x)
|
|
|
|
/*
|
|
* Emulate a CFC1 instruction.
|
|
*/
|
|
static inline void cop1_cfc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
mips_instruction ir)
|
|
{
|
|
u32 fcr31 = ctx->fcr31;
|
|
u32 value = 0;
|
|
|
|
switch (MIPSInst_RD(ir)) {
|
|
case FPCREG_CSR:
|
|
value = fcr31;
|
|
pr_debug("%p gpr[%d]<-csr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
break;
|
|
|
|
case FPCREG_FENR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
value = (fcr31 >> (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
|
|
MIPS_FENR_FS;
|
|
value |= fcr31 & (FPU_CSR_ALL_E | FPU_CSR_RM);
|
|
pr_debug("%p gpr[%d]<-enr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
break;
|
|
|
|
case FPCREG_FEXR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
value = fcr31 & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
|
|
pr_debug("%p gpr[%d]<-exr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
break;
|
|
|
|
case FPCREG_FCCR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
value = (fcr31 >> (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
|
|
MIPS_FCCR_COND0;
|
|
value |= (fcr31 >> (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
|
|
(MIPS_FCCR_CONDX & ~MIPS_FCCR_COND0);
|
|
pr_debug("%p gpr[%d]<-ccr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
break;
|
|
|
|
case FPCREG_RID:
|
|
value = boot_cpu_data.fpu_id;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (MIPSInst_RT(ir))
|
|
xcp->regs[MIPSInst_RT(ir)] = value;
|
|
}
|
|
|
|
/*
|
|
* Emulate a CTC1 instruction.
|
|
*/
|
|
static inline void cop1_ctc(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
mips_instruction ir)
|
|
{
|
|
u32 fcr31 = ctx->fcr31;
|
|
u32 value;
|
|
u32 mask;
|
|
|
|
if (MIPSInst_RT(ir) == 0)
|
|
value = 0;
|
|
else
|
|
value = xcp->regs[MIPSInst_RT(ir)];
|
|
|
|
switch (MIPSInst_RD(ir)) {
|
|
case FPCREG_CSR:
|
|
pr_debug("%p gpr[%d]->csr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
|
|
/* Preserve read-only bits. */
|
|
mask = boot_cpu_data.fpu_msk31;
|
|
fcr31 = (value & ~mask) | (fcr31 & mask);
|
|
break;
|
|
|
|
case FPCREG_FENR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
pr_debug("%p gpr[%d]->enr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
fcr31 &= ~(FPU_CSR_FS | FPU_CSR_ALL_E | FPU_CSR_RM);
|
|
fcr31 |= (value << (FPU_CSR_FS_S - MIPS_FENR_FS_S)) &
|
|
FPU_CSR_FS;
|
|
fcr31 |= value & (FPU_CSR_ALL_E | FPU_CSR_RM);
|
|
break;
|
|
|
|
case FPCREG_FEXR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
pr_debug("%p gpr[%d]->exr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
fcr31 &= ~(FPU_CSR_ALL_X | FPU_CSR_ALL_S);
|
|
fcr31 |= value & (FPU_CSR_ALL_X | FPU_CSR_ALL_S);
|
|
break;
|
|
|
|
case FPCREG_FCCR:
|
|
if (!cpu_has_mips_r)
|
|
break;
|
|
pr_debug("%p gpr[%d]->ccr=%08x\n",
|
|
(void *)xcp->cp0_epc, MIPSInst_RT(ir), value);
|
|
fcr31 &= ~(FPU_CSR_CONDX | FPU_CSR_COND);
|
|
fcr31 |= (value << (FPU_CSR_COND_S - MIPS_FCCR_COND0_S)) &
|
|
FPU_CSR_COND;
|
|
fcr31 |= (value << (FPU_CSR_COND1_S - MIPS_FCCR_COND1_S)) &
|
|
FPU_CSR_CONDX;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
|
|
ctx->fcr31 = fcr31;
|
|
}
|
|
|
|
/*
|
|
* Emulate the single floating point instruction pointed at by EPC.
|
|
* Two instructions if the instruction is in a branch delay slot.
|
|
*/
|
|
|
|
static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
struct mm_decoded_insn dec_insn, void __user **fault_addr)
|
|
{
|
|
unsigned long contpc = xcp->cp0_epc + dec_insn.pc_inc;
|
|
unsigned int cond, cbit, bit0;
|
|
mips_instruction ir;
|
|
int likely, pc_inc;
|
|
union fpureg *fpr;
|
|
u32 __user *wva;
|
|
u64 __user *dva;
|
|
u32 wval;
|
|
u64 dval;
|
|
int sig;
|
|
|
|
/*
|
|
* These are giving gcc a gentle hint about what to expect in
|
|
* dec_inst in order to do better optimization.
|
|
*/
|
|
if (!cpu_has_mmips && dec_insn.micro_mips_mode)
|
|
unreachable();
|
|
|
|
/* XXX NEC Vr54xx bug workaround */
|
|
if (delay_slot(xcp)) {
|
|
if (dec_insn.micro_mips_mode) {
|
|
if (!mm_isBranchInstr(xcp, dec_insn, &contpc))
|
|
clear_delay_slot(xcp);
|
|
} else {
|
|
if (!isBranchInstr(xcp, dec_insn, &contpc))
|
|
clear_delay_slot(xcp);
|
|
}
|
|
}
|
|
|
|
if (delay_slot(xcp)) {
|
|
/*
|
|
* The instruction to be emulated is in a branch delay slot
|
|
* which means that we have to emulate the branch instruction
|
|
* BEFORE we do the cop1 instruction.
|
|
*
|
|
* This branch could be a COP1 branch, but in that case we
|
|
* would have had a trap for that instruction, and would not
|
|
* come through this route.
|
|
*
|
|
* Linux MIPS branch emulator operates on context, updating the
|
|
* cp0_epc.
|
|
*/
|
|
ir = dec_insn.next_insn; /* process delay slot instr */
|
|
pc_inc = dec_insn.next_pc_inc;
|
|
} else {
|
|
ir = dec_insn.insn; /* process current instr */
|
|
pc_inc = dec_insn.pc_inc;
|
|
}
|
|
|
|
/*
|
|
* Since microMIPS FPU instructios are a subset of MIPS32 FPU
|
|
* instructions, we want to convert microMIPS FPU instructions
|
|
* into MIPS32 instructions so that we could reuse all of the
|
|
* FPU emulation code.
|
|
*
|
|
* NOTE: We cannot do this for branch instructions since they
|
|
* are not a subset. Example: Cannot emulate a 16-bit
|
|
* aligned target address with a MIPS32 instruction.
|
|
*/
|
|
if (dec_insn.micro_mips_mode) {
|
|
/*
|
|
* If next instruction is a 16-bit instruction, then it
|
|
* it cannot be a FPU instruction. This could happen
|
|
* since we can be called for non-FPU instructions.
|
|
*/
|
|
if ((pc_inc == 2) ||
|
|
(microMIPS32_to_MIPS32((union mips_instruction *)&ir)
|
|
== SIGILL))
|
|
return SIGILL;
|
|
}
|
|
|
|
emul:
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, xcp, 0);
|
|
MIPS_FPU_EMU_INC_STATS(emulated);
|
|
switch (MIPSInst_OPCODE(ir)) {
|
|
case ldc1_op:
|
|
dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
|
|
MIPSInst_SIMM(ir));
|
|
MIPS_FPU_EMU_INC_STATS(loads);
|
|
|
|
if (!access_ok(dva, sizeof(u64))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = dva;
|
|
return SIGBUS;
|
|
}
|
|
if (__get_user(dval, dva)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = dva;
|
|
return SIGSEGV;
|
|
}
|
|
DITOREG(dval, MIPSInst_RT(ir));
|
|
break;
|
|
|
|
case sdc1_op:
|
|
dva = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
|
|
MIPSInst_SIMM(ir));
|
|
MIPS_FPU_EMU_INC_STATS(stores);
|
|
DIFROMREG(dval, MIPSInst_RT(ir));
|
|
if (!access_ok(dva, sizeof(u64))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = dva;
|
|
return SIGBUS;
|
|
}
|
|
if (__put_user(dval, dva)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = dva;
|
|
return SIGSEGV;
|
|
}
|
|
break;
|
|
|
|
case lwc1_op:
|
|
wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
|
|
MIPSInst_SIMM(ir));
|
|
MIPS_FPU_EMU_INC_STATS(loads);
|
|
if (!access_ok(wva, sizeof(u32))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = wva;
|
|
return SIGBUS;
|
|
}
|
|
if (__get_user(wval, wva)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = wva;
|
|
return SIGSEGV;
|
|
}
|
|
SITOREG(wval, MIPSInst_RT(ir));
|
|
break;
|
|
|
|
case swc1_op:
|
|
wva = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
|
|
MIPSInst_SIMM(ir));
|
|
MIPS_FPU_EMU_INC_STATS(stores);
|
|
SIFROMREG(wval, MIPSInst_RT(ir));
|
|
if (!access_ok(wva, sizeof(u32))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = wva;
|
|
return SIGBUS;
|
|
}
|
|
if (__put_user(wval, wva)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = wva;
|
|
return SIGSEGV;
|
|
}
|
|
break;
|
|
|
|
case cop1_op:
|
|
switch (MIPSInst_RS(ir)) {
|
|
case dmfc_op:
|
|
if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
|
|
return SIGILL;
|
|
|
|
/* copregister fs -> gpr[rt] */
|
|
if (MIPSInst_RT(ir) != 0) {
|
|
DIFROMREG(xcp->regs[MIPSInst_RT(ir)],
|
|
MIPSInst_RD(ir));
|
|
}
|
|
break;
|
|
|
|
case dmtc_op:
|
|
if (!cpu_has_mips_3_4_5 && !cpu_has_mips64)
|
|
return SIGILL;
|
|
|
|
/* copregister fs <- rt */
|
|
DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
|
|
break;
|
|
|
|
case mfhc_op:
|
|
if (!cpu_has_mips_r2_r6)
|
|
return SIGILL;
|
|
|
|
/* copregister rd -> gpr[rt] */
|
|
if (MIPSInst_RT(ir) != 0) {
|
|
SIFROMHREG(xcp->regs[MIPSInst_RT(ir)],
|
|
MIPSInst_RD(ir));
|
|
}
|
|
break;
|
|
|
|
case mthc_op:
|
|
if (!cpu_has_mips_r2_r6)
|
|
return SIGILL;
|
|
|
|
/* copregister rd <- gpr[rt] */
|
|
SITOHREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
|
|
break;
|
|
|
|
case mfc_op:
|
|
/* copregister rd -> gpr[rt] */
|
|
if (MIPSInst_RT(ir) != 0) {
|
|
SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
|
|
MIPSInst_RD(ir));
|
|
}
|
|
break;
|
|
|
|
case mtc_op:
|
|
/* copregister rd <- rt */
|
|
SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
|
|
break;
|
|
|
|
case cfc_op:
|
|
/* cop control register rd -> gpr[rt] */
|
|
cop1_cfc(xcp, ctx, ir);
|
|
break;
|
|
|
|
case ctc_op:
|
|
/* copregister rd <- rt */
|
|
cop1_ctc(xcp, ctx, ir);
|
|
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
|
|
return SIGFPE;
|
|
}
|
|
break;
|
|
|
|
case bc1eqz_op:
|
|
case bc1nez_op:
|
|
if (!cpu_has_mips_r6 || delay_slot(xcp))
|
|
return SIGILL;
|
|
|
|
likely = 0;
|
|
cond = 0;
|
|
fpr = ¤t->thread.fpu.fpr[MIPSInst_RT(ir)];
|
|
bit0 = get_fpr32(fpr, 0) & 0x1;
|
|
switch (MIPSInst_RS(ir)) {
|
|
case bc1eqz_op:
|
|
MIPS_FPU_EMU_INC_STATS(bc1eqz);
|
|
cond = bit0 == 0;
|
|
break;
|
|
case bc1nez_op:
|
|
MIPS_FPU_EMU_INC_STATS(bc1nez);
|
|
cond = bit0 != 0;
|
|
break;
|
|
}
|
|
goto branch_common;
|
|
|
|
case bc_op:
|
|
if (delay_slot(xcp))
|
|
return SIGILL;
|
|
|
|
if (cpu_has_mips_4_5_r)
|
|
cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
|
|
else
|
|
cbit = FPU_CSR_COND;
|
|
cond = ctx->fcr31 & cbit;
|
|
|
|
likely = 0;
|
|
switch (MIPSInst_RT(ir) & 3) {
|
|
case bcfl_op:
|
|
if (cpu_has_mips_2_3_4_5_r)
|
|
likely = 1;
|
|
/* fall through */
|
|
case bcf_op:
|
|
cond = !cond;
|
|
break;
|
|
case bctl_op:
|
|
if (cpu_has_mips_2_3_4_5_r)
|
|
likely = 1;
|
|
/* fall through */
|
|
case bct_op:
|
|
break;
|
|
}
|
|
branch_common:
|
|
MIPS_FPU_EMU_INC_STATS(branches);
|
|
set_delay_slot(xcp);
|
|
if (cond) {
|
|
/*
|
|
* Branch taken: emulate dslot instruction
|
|
*/
|
|
unsigned long bcpc;
|
|
|
|
/*
|
|
* Remember EPC at the branch to point back
|
|
* at so that any delay-slot instruction
|
|
* signal is not silently ignored.
|
|
*/
|
|
bcpc = xcp->cp0_epc;
|
|
xcp->cp0_epc += dec_insn.pc_inc;
|
|
|
|
contpc = MIPSInst_SIMM(ir);
|
|
ir = dec_insn.next_insn;
|
|
if (dec_insn.micro_mips_mode) {
|
|
contpc = (xcp->cp0_epc + (contpc << 1));
|
|
|
|
/* If 16-bit instruction, not FPU. */
|
|
if ((dec_insn.next_pc_inc == 2) ||
|
|
(microMIPS32_to_MIPS32((union mips_instruction *)&ir) == SIGILL)) {
|
|
|
|
/*
|
|
* Since this instruction will
|
|
* be put on the stack with
|
|
* 32-bit words, get around
|
|
* this problem by putting a
|
|
* NOP16 as the second one.
|
|
*/
|
|
if (dec_insn.next_pc_inc == 2)
|
|
ir = (ir & (~0xffff)) | MM_NOP16;
|
|
|
|
/*
|
|
* Single step the non-CP1
|
|
* instruction in the dslot.
|
|
*/
|
|
sig = mips_dsemul(xcp, ir,
|
|
bcpc, contpc);
|
|
if (sig < 0)
|
|
break;
|
|
if (sig)
|
|
xcp->cp0_epc = bcpc;
|
|
/*
|
|
* SIGILL forces out of
|
|
* the emulation loop.
|
|
*/
|
|
return sig ? sig : SIGILL;
|
|
}
|
|
} else
|
|
contpc = (xcp->cp0_epc + (contpc << 2));
|
|
|
|
switch (MIPSInst_OPCODE(ir)) {
|
|
case lwc1_op:
|
|
case swc1_op:
|
|
goto emul;
|
|
|
|
case ldc1_op:
|
|
case sdc1_op:
|
|
if (cpu_has_mips_2_3_4_5_r)
|
|
goto emul;
|
|
|
|
goto bc_sigill;
|
|
|
|
case cop1_op:
|
|
goto emul;
|
|
|
|
case cop1x_op:
|
|
if (cpu_has_mips_4_5_64_r2_r6)
|
|
/* its one of ours */
|
|
goto emul;
|
|
|
|
goto bc_sigill;
|
|
|
|
case spec_op:
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case movc_op:
|
|
if (cpu_has_mips_4_5_r)
|
|
goto emul;
|
|
|
|
goto bc_sigill;
|
|
}
|
|
break;
|
|
|
|
bc_sigill:
|
|
xcp->cp0_epc = bcpc;
|
|
return SIGILL;
|
|
}
|
|
|
|
/*
|
|
* Single step the non-cp1
|
|
* instruction in the dslot
|
|
*/
|
|
sig = mips_dsemul(xcp, ir, bcpc, contpc);
|
|
if (sig < 0)
|
|
break;
|
|
if (sig)
|
|
xcp->cp0_epc = bcpc;
|
|
/* SIGILL forces out of the emulation loop. */
|
|
return sig ? sig : SIGILL;
|
|
} else if (likely) { /* branch not taken */
|
|
/*
|
|
* branch likely nullifies
|
|
* dslot if not taken
|
|
*/
|
|
xcp->cp0_epc += dec_insn.pc_inc;
|
|
contpc += dec_insn.pc_inc;
|
|
/*
|
|
* else continue & execute
|
|
* dslot as normal insn
|
|
*/
|
|
}
|
|
break;
|
|
|
|
default:
|
|
if (!(MIPSInst_RS(ir) & 0x10))
|
|
return SIGILL;
|
|
|
|
/* a real fpu computation instruction */
|
|
sig = fpu_emu(xcp, ctx, ir);
|
|
if (sig)
|
|
return sig;
|
|
}
|
|
break;
|
|
|
|
case cop1x_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
sig = fpux_emu(xcp, ctx, ir, fault_addr);
|
|
if (sig)
|
|
return sig;
|
|
break;
|
|
|
|
case spec_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (MIPSInst_FUNC(ir) != movc_op)
|
|
return SIGILL;
|
|
cond = fpucondbit[MIPSInst_RT(ir) >> 2];
|
|
if (((ctx->fcr31 & cond) != 0) == ((MIPSInst_RT(ir) & 1) != 0))
|
|
xcp->regs[MIPSInst_RD(ir)] =
|
|
xcp->regs[MIPSInst_RS(ir)];
|
|
break;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
/* we did it !! */
|
|
xcp->cp0_epc = contpc;
|
|
clear_delay_slot(xcp);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Conversion table from MIPS compare ops 48-63
|
|
* cond = ieee754dp_cmp(x,y,IEEE754_UN,sig);
|
|
*/
|
|
static const unsigned char cmptab[8] = {
|
|
0, /* cmp_0 (sig) cmp_sf */
|
|
IEEE754_CUN, /* cmp_un (sig) cmp_ngle */
|
|
IEEE754_CEQ, /* cmp_eq (sig) cmp_seq */
|
|
IEEE754_CEQ | IEEE754_CUN, /* cmp_ueq (sig) cmp_ngl */
|
|
IEEE754_CLT, /* cmp_olt (sig) cmp_lt */
|
|
IEEE754_CLT | IEEE754_CUN, /* cmp_ult (sig) cmp_nge */
|
|
IEEE754_CLT | IEEE754_CEQ, /* cmp_ole (sig) cmp_le */
|
|
IEEE754_CLT | IEEE754_CEQ | IEEE754_CUN, /* cmp_ule (sig) cmp_ngt */
|
|
};
|
|
|
|
static const unsigned char negative_cmptab[8] = {
|
|
0, /* Reserved */
|
|
IEEE754_CLT | IEEE754_CGT | IEEE754_CEQ,
|
|
IEEE754_CLT | IEEE754_CGT | IEEE754_CUN,
|
|
IEEE754_CLT | IEEE754_CGT,
|
|
/* Reserved */
|
|
};
|
|
|
|
|
|
/*
|
|
* Additional MIPS4 instructions
|
|
*/
|
|
|
|
#define DEF3OP(name, p, f1, f2, f3) \
|
|
static union ieee754##p fpemu_##p##_##name(union ieee754##p r, \
|
|
union ieee754##p s, union ieee754##p t) \
|
|
{ \
|
|
struct _ieee754_csr ieee754_csr_save; \
|
|
s = f1(s, t); \
|
|
ieee754_csr_save = ieee754_csr; \
|
|
s = f2(s, r); \
|
|
ieee754_csr_save.cx |= ieee754_csr.cx; \
|
|
ieee754_csr_save.sx |= ieee754_csr.sx; \
|
|
s = f3(s); \
|
|
ieee754_csr.cx |= ieee754_csr_save.cx; \
|
|
ieee754_csr.sx |= ieee754_csr_save.sx; \
|
|
return s; \
|
|
}
|
|
|
|
static union ieee754dp fpemu_dp_recip(union ieee754dp d)
|
|
{
|
|
return ieee754dp_div(ieee754dp_one(0), d);
|
|
}
|
|
|
|
static union ieee754dp fpemu_dp_rsqrt(union ieee754dp d)
|
|
{
|
|
return ieee754dp_div(ieee754dp_one(0), ieee754dp_sqrt(d));
|
|
}
|
|
|
|
static union ieee754sp fpemu_sp_recip(union ieee754sp s)
|
|
{
|
|
return ieee754sp_div(ieee754sp_one(0), s);
|
|
}
|
|
|
|
static union ieee754sp fpemu_sp_rsqrt(union ieee754sp s)
|
|
{
|
|
return ieee754sp_div(ieee754sp_one(0), ieee754sp_sqrt(s));
|
|
}
|
|
|
|
DEF3OP(madd, sp, ieee754sp_mul, ieee754sp_add, );
|
|
DEF3OP(msub, sp, ieee754sp_mul, ieee754sp_sub, );
|
|
DEF3OP(nmadd, sp, ieee754sp_mul, ieee754sp_add, ieee754sp_neg);
|
|
DEF3OP(nmsub, sp, ieee754sp_mul, ieee754sp_sub, ieee754sp_neg);
|
|
DEF3OP(madd, dp, ieee754dp_mul, ieee754dp_add, );
|
|
DEF3OP(msub, dp, ieee754dp_mul, ieee754dp_sub, );
|
|
DEF3OP(nmadd, dp, ieee754dp_mul, ieee754dp_add, ieee754dp_neg);
|
|
DEF3OP(nmsub, dp, ieee754dp_mul, ieee754dp_sub, ieee754dp_neg);
|
|
|
|
static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
mips_instruction ir, void __user **fault_addr)
|
|
{
|
|
unsigned int rcsr = 0; /* resulting csr */
|
|
|
|
MIPS_FPU_EMU_INC_STATS(cp1xops);
|
|
|
|
switch (MIPSInst_FMA_FFMT(ir)) {
|
|
case s_fmt:{ /* 0 */
|
|
|
|
union ieee754sp(*handler) (union ieee754sp, union ieee754sp, union ieee754sp);
|
|
union ieee754sp fd, fr, fs, ft;
|
|
u32 __user *va;
|
|
u32 val;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case lwxc1_op:
|
|
va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
MIPS_FPU_EMU_INC_STATS(loads);
|
|
if (!access_ok(va, sizeof(u32))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGBUS;
|
|
}
|
|
if (__get_user(val, va)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGSEGV;
|
|
}
|
|
SITOREG(val, MIPSInst_FD(ir));
|
|
break;
|
|
|
|
case swxc1_op:
|
|
va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
MIPS_FPU_EMU_INC_STATS(stores);
|
|
|
|
SIFROMREG(val, MIPSInst_FS(ir));
|
|
if (!access_ok(va, sizeof(u32))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGBUS;
|
|
}
|
|
if (put_user(val, va)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGSEGV;
|
|
}
|
|
break;
|
|
|
|
case madd_s_op:
|
|
handler = fpemu_sp_madd;
|
|
goto scoptop;
|
|
case msub_s_op:
|
|
handler = fpemu_sp_msub;
|
|
goto scoptop;
|
|
case nmadd_s_op:
|
|
handler = fpemu_sp_nmadd;
|
|
goto scoptop;
|
|
case nmsub_s_op:
|
|
handler = fpemu_sp_nmsub;
|
|
goto scoptop;
|
|
|
|
scoptop:
|
|
SPFROMREG(fr, MIPSInst_FR(ir));
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
fd = (*handler) (fr, fs, ft);
|
|
SPTOREG(fd, MIPSInst_FD(ir));
|
|
|
|
copcsr:
|
|
if (ieee754_cxtest(IEEE754_INEXACT)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
|
|
rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
|
|
rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_OVERFLOW)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
|
|
rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
|
|
rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
}
|
|
|
|
ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
|
|
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
|
|
/*printk ("SIGFPE: FPU csr = %08x\n",
|
|
ctx->fcr31); */
|
|
return SIGFPE;
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case d_fmt:{ /* 1 */
|
|
union ieee754dp(*handler) (union ieee754dp, union ieee754dp, union ieee754dp);
|
|
union ieee754dp fd, fr, fs, ft;
|
|
u64 __user *va;
|
|
u64 val;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case ldxc1_op:
|
|
va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
MIPS_FPU_EMU_INC_STATS(loads);
|
|
if (!access_ok(va, sizeof(u64))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGBUS;
|
|
}
|
|
if (__get_user(val, va)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGSEGV;
|
|
}
|
|
DITOREG(val, MIPSInst_FD(ir));
|
|
break;
|
|
|
|
case sdxc1_op:
|
|
va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] +
|
|
xcp->regs[MIPSInst_FT(ir)]);
|
|
|
|
MIPS_FPU_EMU_INC_STATS(stores);
|
|
DIFROMREG(val, MIPSInst_FS(ir));
|
|
if (!access_ok(va, sizeof(u64))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGBUS;
|
|
}
|
|
if (__put_user(val, va)) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
*fault_addr = va;
|
|
return SIGSEGV;
|
|
}
|
|
break;
|
|
|
|
case madd_d_op:
|
|
handler = fpemu_dp_madd;
|
|
goto dcoptop;
|
|
case msub_d_op:
|
|
handler = fpemu_dp_msub;
|
|
goto dcoptop;
|
|
case nmadd_d_op:
|
|
handler = fpemu_dp_nmadd;
|
|
goto dcoptop;
|
|
case nmsub_d_op:
|
|
handler = fpemu_dp_nmsub;
|
|
goto dcoptop;
|
|
|
|
dcoptop:
|
|
DPFROMREG(fr, MIPSInst_FR(ir));
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
fd = (*handler) (fr, fs, ft);
|
|
DPTOREG(fd, MIPSInst_FD(ir));
|
|
goto copcsr;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case 0x3:
|
|
if (MIPSInst_FUNC(ir) != pfetch_op)
|
|
return SIGILL;
|
|
|
|
/* ignore prefx operation */
|
|
break;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
* Emulate a single COP1 arithmetic instruction.
|
|
*/
|
|
static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
mips_instruction ir)
|
|
{
|
|
int rfmt; /* resulting format */
|
|
unsigned int rcsr = 0; /* resulting csr */
|
|
unsigned int oldrm;
|
|
unsigned int cbit;
|
|
unsigned int cond;
|
|
union {
|
|
union ieee754dp d;
|
|
union ieee754sp s;
|
|
int w;
|
|
s64 l;
|
|
} rv; /* resulting value */
|
|
u64 bits;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(cp1ops);
|
|
switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) {
|
|
case s_fmt: { /* 0 */
|
|
union {
|
|
union ieee754sp(*b) (union ieee754sp, union ieee754sp);
|
|
union ieee754sp(*u) (union ieee754sp);
|
|
} handler;
|
|
union ieee754sp fd, fs, ft;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
/* binary ops */
|
|
case fadd_op:
|
|
MIPS_FPU_EMU_INC_STATS(add_s);
|
|
handler.b = ieee754sp_add;
|
|
goto scopbop;
|
|
case fsub_op:
|
|
MIPS_FPU_EMU_INC_STATS(sub_s);
|
|
handler.b = ieee754sp_sub;
|
|
goto scopbop;
|
|
case fmul_op:
|
|
MIPS_FPU_EMU_INC_STATS(mul_s);
|
|
handler.b = ieee754sp_mul;
|
|
goto scopbop;
|
|
case fdiv_op:
|
|
MIPS_FPU_EMU_INC_STATS(div_s);
|
|
handler.b = ieee754sp_div;
|
|
goto scopbop;
|
|
|
|
/* unary ops */
|
|
case fsqrt_op:
|
|
if (!cpu_has_mips_2_3_4_5_r)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(sqrt_s);
|
|
handler.u = ieee754sp_sqrt;
|
|
goto scopuop;
|
|
|
|
/*
|
|
* Note that on some MIPS IV implementations such as the
|
|
* R5000 and R8000 the FSQRT and FRECIP instructions do not
|
|
* achieve full IEEE-754 accuracy - however this emulator does.
|
|
*/
|
|
case frsqrt_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(rsqrt_s);
|
|
handler.u = fpemu_sp_rsqrt;
|
|
goto scopuop;
|
|
|
|
case frecip_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(recip_s);
|
|
handler.u = fpemu_sp_recip;
|
|
goto scopuop;
|
|
|
|
case fmovc_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
cond = fpucondbit[MIPSInst_FT(ir) >> 2];
|
|
if (((ctx->fcr31 & cond) != 0) !=
|
|
((MIPSInst_FT(ir) & 1) != 0))
|
|
return 0;
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fmovz_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (xcp->regs[MIPSInst_FT(ir)] != 0)
|
|
return 0;
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fmovn_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (xcp->regs[MIPSInst_FT(ir)] == 0)
|
|
return 0;
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fseleqz_op:
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(seleqz_s);
|
|
SPFROMREG(rv.s, MIPSInst_FT(ir));
|
|
if (rv.w & 0x1)
|
|
rv.w = 0;
|
|
else
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fselnez_op:
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(selnez_s);
|
|
SPFROMREG(rv.s, MIPSInst_FT(ir));
|
|
if (rv.w & 0x1)
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
else
|
|
rv.w = 0;
|
|
break;
|
|
|
|
case fmaddf_op: {
|
|
union ieee754sp ft, fs, fd;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(maddf_s);
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(fd, MIPSInst_FD(ir));
|
|
rv.s = ieee754sp_maddf(fd, fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmsubf_op: {
|
|
union ieee754sp ft, fs, fd;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(msubf_s);
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(fd, MIPSInst_FD(ir));
|
|
rv.s = ieee754sp_msubf(fd, fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case frint_op: {
|
|
union ieee754sp fs;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(rint_s);
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_rint(fs);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fclass_op: {
|
|
union ieee754sp fs;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(class_s);
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.w = ieee754sp_2008class(fs);
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmin_op: {
|
|
union ieee754sp fs, ft;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(min_s);
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fmin(fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmina_op: {
|
|
union ieee754sp fs, ft;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(mina_s);
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fmina(fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmax_op: {
|
|
union ieee754sp fs, ft;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(max_s);
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fmax(fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmaxa_op: {
|
|
union ieee754sp fs, ft;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(maxa_s);
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fmaxa(fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fabs_op:
|
|
MIPS_FPU_EMU_INC_STATS(abs_s);
|
|
handler.u = ieee754sp_abs;
|
|
goto scopuop;
|
|
|
|
case fneg_op:
|
|
MIPS_FPU_EMU_INC_STATS(neg_s);
|
|
handler.u = ieee754sp_neg;
|
|
goto scopuop;
|
|
|
|
case fmov_op:
|
|
/* an easy one */
|
|
MIPS_FPU_EMU_INC_STATS(mov_s);
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
goto copcsr;
|
|
|
|
/* binary op on handler */
|
|
scopbop:
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
|
|
rv.s = (*handler.b) (fs, ft);
|
|
goto copcsr;
|
|
scopuop:
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = (*handler.u) (fs);
|
|
goto copcsr;
|
|
copcsr:
|
|
if (ieee754_cxtest(IEEE754_INEXACT)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_inexact);
|
|
rcsr |= FPU_CSR_INE_X | FPU_CSR_INE_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_UNDERFLOW)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_underflow);
|
|
rcsr |= FPU_CSR_UDF_X | FPU_CSR_UDF_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_OVERFLOW)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_overflow);
|
|
rcsr |= FPU_CSR_OVF_X | FPU_CSR_OVF_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_ZERO_DIVIDE)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_zerodiv);
|
|
rcsr |= FPU_CSR_DIV_X | FPU_CSR_DIV_S;
|
|
}
|
|
if (ieee754_cxtest(IEEE754_INVALID_OPERATION)) {
|
|
MIPS_FPU_EMU_INC_STATS(ieee754_invalidop);
|
|
rcsr |= FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
}
|
|
break;
|
|
|
|
/* unary conv ops */
|
|
case fcvts_op:
|
|
return SIGILL; /* not defined */
|
|
|
|
case fcvtd_op:
|
|
MIPS_FPU_EMU_INC_STATS(cvt_d_s);
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fsp(fs);
|
|
rfmt = d_fmt;
|
|
goto copcsr;
|
|
|
|
case fcvtw_op:
|
|
MIPS_FPU_EMU_INC_STATS(cvt_w_s);
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.w = ieee754sp_tint(fs);
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
|
|
case fround_op:
|
|
case ftrunc_op:
|
|
case fceil_op:
|
|
case ffloor_op:
|
|
if (!cpu_has_mips_2_3_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (MIPSInst_FUNC(ir) == fceil_op)
|
|
MIPS_FPU_EMU_INC_STATS(ceil_w_s);
|
|
if (MIPSInst_FUNC(ir) == ffloor_op)
|
|
MIPS_FPU_EMU_INC_STATS(floor_w_s);
|
|
if (MIPSInst_FUNC(ir) == fround_op)
|
|
MIPS_FPU_EMU_INC_STATS(round_w_s);
|
|
if (MIPSInst_FUNC(ir) == ftrunc_op)
|
|
MIPS_FPU_EMU_INC_STATS(trunc_w_s);
|
|
|
|
oldrm = ieee754_csr.rm;
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = MIPSInst_FUNC(ir);
|
|
rv.w = ieee754sp_tint(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
|
|
case fsel_op:
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(sel_s);
|
|
SPFROMREG(fd, MIPSInst_FD(ir));
|
|
if (fd.bits & 0x1)
|
|
SPFROMREG(rv.s, MIPSInst_FT(ir));
|
|
else
|
|
SPFROMREG(rv.s, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fcvtl_op:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(cvt_l_s);
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.l = ieee754sp_tlong(fs);
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
|
|
case froundl_op:
|
|
case ftruncl_op:
|
|
case fceill_op:
|
|
case ffloorl_op:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
if (MIPSInst_FUNC(ir) == fceill_op)
|
|
MIPS_FPU_EMU_INC_STATS(ceil_l_s);
|
|
if (MIPSInst_FUNC(ir) == ffloorl_op)
|
|
MIPS_FPU_EMU_INC_STATS(floor_l_s);
|
|
if (MIPSInst_FUNC(ir) == froundl_op)
|
|
MIPS_FPU_EMU_INC_STATS(round_l_s);
|
|
if (MIPSInst_FUNC(ir) == ftruncl_op)
|
|
MIPS_FPU_EMU_INC_STATS(trunc_l_s);
|
|
|
|
oldrm = ieee754_csr.rm;
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = MIPSInst_FUNC(ir);
|
|
rv.l = ieee754sp_tlong(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
|
|
default:
|
|
if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
|
|
unsigned int cmpop;
|
|
union ieee754sp fs, ft;
|
|
|
|
cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
rv.w = ieee754sp_cmp(fs, ft,
|
|
cmptab[cmpop & 0x7], cmpop & 0x8);
|
|
rfmt = -1;
|
|
if ((cmpop & 0x8) && ieee754_cxtest
|
|
(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
|
|
} else
|
|
return SIGILL;
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case d_fmt: {
|
|
union ieee754dp fd, fs, ft;
|
|
union {
|
|
union ieee754dp(*b) (union ieee754dp, union ieee754dp);
|
|
union ieee754dp(*u) (union ieee754dp);
|
|
} handler;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
/* binary ops */
|
|
case fadd_op:
|
|
MIPS_FPU_EMU_INC_STATS(add_d);
|
|
handler.b = ieee754dp_add;
|
|
goto dcopbop;
|
|
case fsub_op:
|
|
MIPS_FPU_EMU_INC_STATS(sub_d);
|
|
handler.b = ieee754dp_sub;
|
|
goto dcopbop;
|
|
case fmul_op:
|
|
MIPS_FPU_EMU_INC_STATS(mul_d);
|
|
handler.b = ieee754dp_mul;
|
|
goto dcopbop;
|
|
case fdiv_op:
|
|
MIPS_FPU_EMU_INC_STATS(div_d);
|
|
handler.b = ieee754dp_div;
|
|
goto dcopbop;
|
|
|
|
/* unary ops */
|
|
case fsqrt_op:
|
|
if (!cpu_has_mips_2_3_4_5_r)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(sqrt_d);
|
|
handler.u = ieee754dp_sqrt;
|
|
goto dcopuop;
|
|
/*
|
|
* Note that on some MIPS IV implementations such as the
|
|
* R5000 and R8000 the FSQRT and FRECIP instructions do not
|
|
* achieve full IEEE-754 accuracy - however this emulator does.
|
|
*/
|
|
case frsqrt_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(rsqrt_d);
|
|
handler.u = fpemu_dp_rsqrt;
|
|
goto dcopuop;
|
|
case frecip_op:
|
|
if (!cpu_has_mips_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(recip_d);
|
|
handler.u = fpemu_dp_recip;
|
|
goto dcopuop;
|
|
case fmovc_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
cond = fpucondbit[MIPSInst_FT(ir) >> 2];
|
|
if (((ctx->fcr31 & cond) != 0) !=
|
|
((MIPSInst_FT(ir) & 1) != 0))
|
|
return 0;
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
case fmovz_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (xcp->regs[MIPSInst_FT(ir)] != 0)
|
|
return 0;
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
case fmovn_op:
|
|
if (!cpu_has_mips_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (xcp->regs[MIPSInst_FT(ir)] == 0)
|
|
return 0;
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fseleqz_op:
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(seleqz_d);
|
|
DPFROMREG(rv.d, MIPSInst_FT(ir));
|
|
if (rv.l & 0x1)
|
|
rv.l = 0;
|
|
else
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fselnez_op:
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(selnez_d);
|
|
DPFROMREG(rv.d, MIPSInst_FT(ir));
|
|
if (rv.l & 0x1)
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
else
|
|
rv.l = 0;
|
|
break;
|
|
|
|
case fmaddf_op: {
|
|
union ieee754dp ft, fs, fd;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(maddf_d);
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(fd, MIPSInst_FD(ir));
|
|
rv.d = ieee754dp_maddf(fd, fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmsubf_op: {
|
|
union ieee754dp ft, fs, fd;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(msubf_d);
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(fd, MIPSInst_FD(ir));
|
|
rv.d = ieee754dp_msubf(fd, fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case frint_op: {
|
|
union ieee754dp fs;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(rint_d);
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_rint(fs);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fclass_op: {
|
|
union ieee754dp fs;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(class_d);
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.l = ieee754dp_2008class(fs);
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmin_op: {
|
|
union ieee754dp fs, ft;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(min_d);
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fmin(fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmina_op: {
|
|
union ieee754dp fs, ft;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(mina_d);
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fmina(fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmax_op: {
|
|
union ieee754dp fs, ft;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(max_d);
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fmax(fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fmaxa_op: {
|
|
union ieee754dp fs, ft;
|
|
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(maxa_d);
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fmaxa(fs, ft);
|
|
goto copcsr;
|
|
}
|
|
|
|
case fabs_op:
|
|
MIPS_FPU_EMU_INC_STATS(abs_d);
|
|
handler.u = ieee754dp_abs;
|
|
goto dcopuop;
|
|
|
|
case fneg_op:
|
|
MIPS_FPU_EMU_INC_STATS(neg_d);
|
|
handler.u = ieee754dp_neg;
|
|
goto dcopuop;
|
|
|
|
case fmov_op:
|
|
/* an easy one */
|
|
MIPS_FPU_EMU_INC_STATS(mov_d);
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
goto copcsr;
|
|
|
|
/* binary op on handler */
|
|
dcopbop:
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
|
|
rv.d = (*handler.b) (fs, ft);
|
|
goto copcsr;
|
|
dcopuop:
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = (*handler.u) (fs);
|
|
goto copcsr;
|
|
|
|
/*
|
|
* unary conv ops
|
|
*/
|
|
case fcvts_op:
|
|
MIPS_FPU_EMU_INC_STATS(cvt_s_d);
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fdp(fs);
|
|
rfmt = s_fmt;
|
|
goto copcsr;
|
|
|
|
case fcvtd_op:
|
|
return SIGILL; /* not defined */
|
|
|
|
case fcvtw_op:
|
|
MIPS_FPU_EMU_INC_STATS(cvt_w_d);
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.w = ieee754dp_tint(fs); /* wrong */
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
|
|
case fround_op:
|
|
case ftrunc_op:
|
|
case fceil_op:
|
|
case ffloor_op:
|
|
if (!cpu_has_mips_2_3_4_5_r)
|
|
return SIGILL;
|
|
|
|
if (MIPSInst_FUNC(ir) == fceil_op)
|
|
MIPS_FPU_EMU_INC_STATS(ceil_w_d);
|
|
if (MIPSInst_FUNC(ir) == ffloor_op)
|
|
MIPS_FPU_EMU_INC_STATS(floor_w_d);
|
|
if (MIPSInst_FUNC(ir) == fround_op)
|
|
MIPS_FPU_EMU_INC_STATS(round_w_d);
|
|
if (MIPSInst_FUNC(ir) == ftrunc_op)
|
|
MIPS_FPU_EMU_INC_STATS(trunc_w_d);
|
|
|
|
oldrm = ieee754_csr.rm;
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = MIPSInst_FUNC(ir);
|
|
rv.w = ieee754dp_tint(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = w_fmt;
|
|
goto copcsr;
|
|
|
|
case fsel_op:
|
|
if (!cpu_has_mips_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(sel_d);
|
|
DPFROMREG(fd, MIPSInst_FD(ir));
|
|
if (fd.bits & 0x1)
|
|
DPFROMREG(rv.d, MIPSInst_FT(ir));
|
|
else
|
|
DPFROMREG(rv.d, MIPSInst_FS(ir));
|
|
break;
|
|
|
|
case fcvtl_op:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
MIPS_FPU_EMU_INC_STATS(cvt_l_d);
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.l = ieee754dp_tlong(fs);
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
|
|
case froundl_op:
|
|
case ftruncl_op:
|
|
case fceill_op:
|
|
case ffloorl_op:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
if (MIPSInst_FUNC(ir) == fceill_op)
|
|
MIPS_FPU_EMU_INC_STATS(ceil_l_d);
|
|
if (MIPSInst_FUNC(ir) == ffloorl_op)
|
|
MIPS_FPU_EMU_INC_STATS(floor_l_d);
|
|
if (MIPSInst_FUNC(ir) == froundl_op)
|
|
MIPS_FPU_EMU_INC_STATS(round_l_d);
|
|
if (MIPSInst_FUNC(ir) == ftruncl_op)
|
|
MIPS_FPU_EMU_INC_STATS(trunc_l_d);
|
|
|
|
oldrm = ieee754_csr.rm;
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
ieee754_csr.rm = MIPSInst_FUNC(ir);
|
|
rv.l = ieee754dp_tlong(fs);
|
|
ieee754_csr.rm = oldrm;
|
|
rfmt = l_fmt;
|
|
goto copcsr;
|
|
|
|
default:
|
|
if (!NO_R6EMU && MIPSInst_FUNC(ir) >= fcmp_op) {
|
|
unsigned int cmpop;
|
|
union ieee754dp fs, ft;
|
|
|
|
cmpop = MIPSInst_FUNC(ir) - fcmp_op;
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
rv.w = ieee754dp_cmp(fs, ft,
|
|
cmptab[cmpop & 0x7], cmpop & 0x8);
|
|
rfmt = -1;
|
|
if ((cmpop & 0x8)
|
|
&&
|
|
ieee754_cxtest
|
|
(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
|
|
}
|
|
else {
|
|
return SIGILL;
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case w_fmt: {
|
|
union ieee754dp fs;
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case fcvts_op:
|
|
/* convert word to single precision real */
|
|
MIPS_FPU_EMU_INC_STATS(cvt_s_w);
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.s = ieee754sp_fint(fs.bits);
|
|
rfmt = s_fmt;
|
|
goto copcsr;
|
|
case fcvtd_op:
|
|
/* convert word to double precision real */
|
|
MIPS_FPU_EMU_INC_STATS(cvt_d_w);
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
rv.d = ieee754dp_fint(fs.bits);
|
|
rfmt = d_fmt;
|
|
goto copcsr;
|
|
default: {
|
|
/* Emulating the new CMP.condn.fmt R6 instruction */
|
|
#define CMPOP_MASK 0x7
|
|
#define SIGN_BIT (0x1 << 3)
|
|
#define PREDICATE_BIT (0x1 << 4)
|
|
|
|
int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
|
|
int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
|
|
union ieee754sp fs, ft;
|
|
|
|
/* This is an R6 only instruction */
|
|
if (!cpu_has_mips_r6 ||
|
|
(MIPSInst_FUNC(ir) & 0x20))
|
|
return SIGILL;
|
|
|
|
if (!sig) {
|
|
if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
|
|
switch (cmpop) {
|
|
case 0:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_af_s);
|
|
break;
|
|
case 1:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_un_s);
|
|
break;
|
|
case 2:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_eq_s);
|
|
break;
|
|
case 3:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_ueq_s);
|
|
break;
|
|
case 4:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_lt_s);
|
|
break;
|
|
case 5:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_ult_s);
|
|
break;
|
|
case 6:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_le_s);
|
|
break;
|
|
case 7:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_ule_s);
|
|
break;
|
|
}
|
|
} else {
|
|
switch (cmpop) {
|
|
case 1:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_or_s);
|
|
break;
|
|
case 2:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_une_s);
|
|
break;
|
|
case 3:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_ne_s);
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
|
|
switch (cmpop) {
|
|
case 0:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_saf_s);
|
|
break;
|
|
case 1:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sun_s);
|
|
break;
|
|
case 2:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_seq_s);
|
|
break;
|
|
case 3:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sueq_s);
|
|
break;
|
|
case 4:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_slt_s);
|
|
break;
|
|
case 5:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sult_s);
|
|
break;
|
|
case 6:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sle_s);
|
|
break;
|
|
case 7:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sule_s);
|
|
break;
|
|
}
|
|
} else {
|
|
switch (cmpop) {
|
|
case 1:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sor_s);
|
|
break;
|
|
case 2:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sune_s);
|
|
break;
|
|
case 3:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sne_s);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* fmt is w_fmt for single precision so fix it */
|
|
rfmt = s_fmt;
|
|
/* default to false */
|
|
rv.w = 0;
|
|
|
|
/* CMP.condn.S */
|
|
SPFROMREG(fs, MIPSInst_FS(ir));
|
|
SPFROMREG(ft, MIPSInst_FT(ir));
|
|
|
|
/* positive predicates */
|
|
if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
|
|
if (ieee754sp_cmp(fs, ft, cmptab[cmpop],
|
|
sig))
|
|
rv.w = -1; /* true, all 1s */
|
|
if ((sig) &&
|
|
ieee754_cxtest(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
} else {
|
|
/* negative predicates */
|
|
switch (cmpop) {
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
if (ieee754sp_cmp(fs, ft,
|
|
negative_cmptab[cmpop],
|
|
sig))
|
|
rv.w = -1; /* true, all 1s */
|
|
if (sig &&
|
|
ieee754_cxtest(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
break;
|
|
default:
|
|
/* Reserved R6 ops */
|
|
return SIGILL;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
case l_fmt:
|
|
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
DIFROMREG(bits, MIPSInst_FS(ir));
|
|
|
|
switch (MIPSInst_FUNC(ir)) {
|
|
case fcvts_op:
|
|
/* convert long to single precision real */
|
|
MIPS_FPU_EMU_INC_STATS(cvt_s_l);
|
|
rv.s = ieee754sp_flong(bits);
|
|
rfmt = s_fmt;
|
|
goto copcsr;
|
|
case fcvtd_op:
|
|
/* convert long to double precision real */
|
|
MIPS_FPU_EMU_INC_STATS(cvt_d_l);
|
|
rv.d = ieee754dp_flong(bits);
|
|
rfmt = d_fmt;
|
|
goto copcsr;
|
|
default: {
|
|
/* Emulating the new CMP.condn.fmt R6 instruction */
|
|
int cmpop = MIPSInst_FUNC(ir) & CMPOP_MASK;
|
|
int sig = MIPSInst_FUNC(ir) & SIGN_BIT;
|
|
union ieee754dp fs, ft;
|
|
|
|
if (!cpu_has_mips_r6 ||
|
|
(MIPSInst_FUNC(ir) & 0x20))
|
|
return SIGILL;
|
|
|
|
if (!sig) {
|
|
if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
|
|
switch (cmpop) {
|
|
case 0:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_af_d);
|
|
break;
|
|
case 1:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_un_d);
|
|
break;
|
|
case 2:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_eq_d);
|
|
break;
|
|
case 3:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_ueq_d);
|
|
break;
|
|
case 4:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_lt_d);
|
|
break;
|
|
case 5:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_ult_d);
|
|
break;
|
|
case 6:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_le_d);
|
|
break;
|
|
case 7:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_ule_d);
|
|
break;
|
|
}
|
|
} else {
|
|
switch (cmpop) {
|
|
case 1:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_or_d);
|
|
break;
|
|
case 2:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_une_d);
|
|
break;
|
|
case 3:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_ne_d);
|
|
break;
|
|
}
|
|
}
|
|
} else {
|
|
if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
|
|
switch (cmpop) {
|
|
case 0:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_saf_d);
|
|
break;
|
|
case 1:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sun_d);
|
|
break;
|
|
case 2:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_seq_d);
|
|
break;
|
|
case 3:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sueq_d);
|
|
break;
|
|
case 4:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_slt_d);
|
|
break;
|
|
case 5:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sult_d);
|
|
break;
|
|
case 6:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sle_d);
|
|
break;
|
|
case 7:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sule_d);
|
|
break;
|
|
}
|
|
} else {
|
|
switch (cmpop) {
|
|
case 1:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sor_d);
|
|
break;
|
|
case 2:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sune_d);
|
|
break;
|
|
case 3:
|
|
MIPS_FPU_EMU_INC_STATS(cmp_sne_d);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* fmt is l_fmt for double precision so fix it */
|
|
rfmt = d_fmt;
|
|
/* default to false */
|
|
rv.l = 0;
|
|
|
|
/* CMP.condn.D */
|
|
DPFROMREG(fs, MIPSInst_FS(ir));
|
|
DPFROMREG(ft, MIPSInst_FT(ir));
|
|
|
|
/* positive predicates */
|
|
if (!(MIPSInst_FUNC(ir) & PREDICATE_BIT)) {
|
|
if (ieee754dp_cmp(fs, ft,
|
|
cmptab[cmpop], sig))
|
|
rv.l = -1LL; /* true, all 1s */
|
|
if (sig &&
|
|
ieee754_cxtest(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
} else {
|
|
/* negative predicates */
|
|
switch (cmpop) {
|
|
case 1:
|
|
case 2:
|
|
case 3:
|
|
if (ieee754dp_cmp(fs, ft,
|
|
negative_cmptab[cmpop],
|
|
sig))
|
|
rv.l = -1LL; /* true, all 1s */
|
|
if (sig &&
|
|
ieee754_cxtest(IEEE754_INVALID_OPERATION))
|
|
rcsr = FPU_CSR_INV_X | FPU_CSR_INV_S;
|
|
else
|
|
goto copcsr;
|
|
break;
|
|
default:
|
|
/* Reserved R6 ops */
|
|
return SIGILL;
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
/*
|
|
* Update the fpu CSR register for this operation.
|
|
* If an exception is required, generate a tidy SIGFPE exception,
|
|
* without updating the result register.
|
|
* Note: cause exception bits do not accumulate, they are rewritten
|
|
* for each op; only the flag/sticky bits accumulate.
|
|
*/
|
|
ctx->fcr31 = (ctx->fcr31 & ~FPU_CSR_ALL_X) | rcsr;
|
|
if ((ctx->fcr31 >> 5) & ctx->fcr31 & FPU_CSR_ALL_E) {
|
|
/*printk ("SIGFPE: FPU csr = %08x\n",ctx->fcr31); */
|
|
return SIGFPE;
|
|
}
|
|
|
|
/*
|
|
* Now we can safely write the result back to the register file.
|
|
*/
|
|
switch (rfmt) {
|
|
case -1:
|
|
|
|
if (cpu_has_mips_4_5_r)
|
|
cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
|
|
else
|
|
cbit = FPU_CSR_COND;
|
|
if (rv.w)
|
|
ctx->fcr31 |= cbit;
|
|
else
|
|
ctx->fcr31 &= ~cbit;
|
|
break;
|
|
|
|
case d_fmt:
|
|
DPTOREG(rv.d, MIPSInst_FD(ir));
|
|
break;
|
|
case s_fmt:
|
|
SPTOREG(rv.s, MIPSInst_FD(ir));
|
|
break;
|
|
case w_fmt:
|
|
SITOREG(rv.w, MIPSInst_FD(ir));
|
|
break;
|
|
case l_fmt:
|
|
if (!cpu_has_mips_3_4_5_64_r2_r6)
|
|
return SIGILL;
|
|
|
|
DITOREG(rv.l, MIPSInst_FD(ir));
|
|
break;
|
|
default:
|
|
return SIGILL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Emulate FPU instructions.
|
|
*
|
|
* If we use FPU hardware, then we have been typically called to handle
|
|
* an unimplemented operation, such as where an operand is a NaN or
|
|
* denormalized. In that case exit the emulation loop after a single
|
|
* iteration so as to let hardware execute any subsequent instructions.
|
|
*
|
|
* If we have no FPU hardware or it has been disabled, then continue
|
|
* emulating floating-point instructions until one of these conditions
|
|
* has occurred:
|
|
*
|
|
* - a non-FPU instruction has been encountered,
|
|
*
|
|
* - an attempt to emulate has ended with a signal,
|
|
*
|
|
* - the ISA mode has been switched.
|
|
*
|
|
* We need to terminate the emulation loop if we got switched to the
|
|
* MIPS16 mode, whether supported or not, so that we do not attempt
|
|
* to emulate a MIPS16 instruction as a regular MIPS FPU instruction.
|
|
* Similarly if we got switched to the microMIPS mode and only the
|
|
* regular MIPS mode is supported, so that we do not attempt to emulate
|
|
* a microMIPS instruction as a regular MIPS FPU instruction. Or if
|
|
* we got switched to the regular MIPS mode and only the microMIPS mode
|
|
* is supported, so that we do not attempt to emulate a regular MIPS
|
|
* instruction that should cause an Address Error exception instead.
|
|
* For simplicity we always terminate upon an ISA mode switch.
|
|
*/
|
|
int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx,
|
|
int has_fpu, void __user **fault_addr)
|
|
{
|
|
unsigned long oldepc, prevepc;
|
|
struct mm_decoded_insn dec_insn;
|
|
u16 instr[4];
|
|
u16 *instr_ptr;
|
|
int sig = 0;
|
|
|
|
/*
|
|
* Initialize context if it hasn't been used already, otherwise ensure
|
|
* it has been saved to struct thread_struct.
|
|
*/
|
|
if (!init_fp_ctx(current))
|
|
lose_fpu(1);
|
|
|
|
oldepc = xcp->cp0_epc;
|
|
do {
|
|
prevepc = xcp->cp0_epc;
|
|
|
|
if (get_isa16_mode(prevepc) && cpu_has_mmips) {
|
|
/*
|
|
* Get next 2 microMIPS instructions and convert them
|
|
* into 32-bit instructions.
|
|
*/
|
|
if ((get_user(instr[0], (u16 __user *)msk_isa16_mode(xcp->cp0_epc))) ||
|
|
(get_user(instr[1], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 2))) ||
|
|
(get_user(instr[2], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 4))) ||
|
|
(get_user(instr[3], (u16 __user *)msk_isa16_mode(xcp->cp0_epc + 6)))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
return SIGBUS;
|
|
}
|
|
instr_ptr = instr;
|
|
|
|
/* Get first instruction. */
|
|
if (mm_insn_16bit(*instr_ptr)) {
|
|
/* Duplicate the half-word. */
|
|
dec_insn.insn = (*instr_ptr << 16) |
|
|
(*instr_ptr);
|
|
/* 16-bit instruction. */
|
|
dec_insn.pc_inc = 2;
|
|
instr_ptr += 1;
|
|
} else {
|
|
dec_insn.insn = (*instr_ptr << 16) |
|
|
*(instr_ptr+1);
|
|
/* 32-bit instruction. */
|
|
dec_insn.pc_inc = 4;
|
|
instr_ptr += 2;
|
|
}
|
|
/* Get second instruction. */
|
|
if (mm_insn_16bit(*instr_ptr)) {
|
|
/* Duplicate the half-word. */
|
|
dec_insn.next_insn = (*instr_ptr << 16) |
|
|
(*instr_ptr);
|
|
/* 16-bit instruction. */
|
|
dec_insn.next_pc_inc = 2;
|
|
} else {
|
|
dec_insn.next_insn = (*instr_ptr << 16) |
|
|
*(instr_ptr+1);
|
|
/* 32-bit instruction. */
|
|
dec_insn.next_pc_inc = 4;
|
|
}
|
|
dec_insn.micro_mips_mode = 1;
|
|
} else {
|
|
if ((get_user(dec_insn.insn,
|
|
(mips_instruction __user *) xcp->cp0_epc)) ||
|
|
(get_user(dec_insn.next_insn,
|
|
(mips_instruction __user *)(xcp->cp0_epc+4)))) {
|
|
MIPS_FPU_EMU_INC_STATS(errors);
|
|
return SIGBUS;
|
|
}
|
|
dec_insn.pc_inc = 4;
|
|
dec_insn.next_pc_inc = 4;
|
|
dec_insn.micro_mips_mode = 0;
|
|
}
|
|
|
|
if ((dec_insn.insn == 0) ||
|
|
((dec_insn.pc_inc == 2) &&
|
|
((dec_insn.insn & 0xffff) == MM_NOP16)))
|
|
xcp->cp0_epc += dec_insn.pc_inc; /* Skip NOPs */
|
|
else {
|
|
/*
|
|
* The 'ieee754_csr' is an alias of ctx->fcr31.
|
|
* No need to copy ctx->fcr31 to ieee754_csr.
|
|
*/
|
|
sig = cop1Emulate(xcp, ctx, dec_insn, fault_addr);
|
|
}
|
|
|
|
if (has_fpu)
|
|
break;
|
|
if (sig)
|
|
break;
|
|
/*
|
|
* We have to check for the ISA bit explicitly here,
|
|
* because `get_isa16_mode' may return 0 if support
|
|
* for code compression has been globally disabled,
|
|
* or otherwise we may produce the wrong signal or
|
|
* even proceed successfully where we must not.
|
|
*/
|
|
if ((xcp->cp0_epc ^ prevepc) & 0x1)
|
|
break;
|
|
|
|
cond_resched();
|
|
} while (xcp->cp0_epc > prevepc);
|
|
|
|
/* SIGILL indicates a non-fpu instruction */
|
|
if (sig == SIGILL && xcp->cp0_epc != oldepc)
|
|
/* but if EPC has advanced, then ignore it */
|
|
sig = 0;
|
|
|
|
return sig;
|
|
}
|