ab8dff4b71
commit d51f86cfd8e378d4907958db77da3074f6dce3ba upstream.
The dssall ("Data Stream Stop All") instruction is obsolete altogether
with other Data Cache Instructions since ISA 2.03 (year 2006).
LLVM IAS does not support it but PPC970 seems to be using it.
This switches dssall to .long as there is no much point in fixing LLVM.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20211221055904.555763-6-aik@ozlabs.ru
[sudip: adjust context]
Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Common implementation of switch_mm_irqs_off
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*
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* Copyright IBM Corp. 2017
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*/
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#include <linux/mm.h>
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#include <linux/cpu.h>
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#include <linux/sched/mm.h>
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#include <asm/mmu_context.h>
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#include <asm/pgalloc.h>
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#if defined(CONFIG_PPC32)
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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/* 32-bit keeps track of the current PGDIR in the thread struct */
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tsk->thread.pgdir = mm->pgd;
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}
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#elif defined(CONFIG_PPC_BOOK3E_64)
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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/* 64-bit Book3E keeps track of current PGD in the PACA */
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get_paca()->pgd = mm->pgd;
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}
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#else
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static inline void switch_mm_pgdir(struct task_struct *tsk,
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struct mm_struct *mm) { }
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#endif
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void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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bool new_on_cpu = false;
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/* Mark this context has been used on the new CPU */
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if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
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inc_mm_active_cpus(next);
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/*
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* This full barrier orders the store to the cpumask above vs
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* a subsequent operation which allows this CPU to begin loading
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* translations for next.
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*
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* When using the radix MMU that operation is the load of the
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* MMU context id, which is then moved to SPRN_PID.
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*
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* For the hash MMU it is either the first load from slb_cache
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* in switch_slb(), and/or the store of paca->mm_ctx_id in
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* copy_mm_to_paca().
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*
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* On the other side, the barrier is in mm/tlb-radix.c for
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* radix which orders earlier stores to clear the PTEs vs
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* the load of mm_cpumask. And pte_xchg which does the same
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* thing for hash.
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*
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* This full barrier is needed by membarrier when switching
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* between processes after store to rq->curr, before user-space
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* memory accesses.
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*/
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smp_mb();
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new_on_cpu = true;
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}
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/* Some subarchs need to track the PGD elsewhere */
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switch_mm_pgdir(tsk, next);
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/* Nothing else to do if we aren't actually switching */
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if (prev == next)
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return;
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/*
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* We must stop all altivec streams before changing the HW
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* context
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*/
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if (cpu_has_feature(CPU_FTR_ALTIVEC))
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asm volatile (PPC_DSSALL);
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if (new_on_cpu)
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radix_kvm_prefetch_workaround(next);
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else
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membarrier_arch_switch_mm(prev, next, tsk);
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/*
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* The actual HW switching method differs between the various
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* sub architectures. Out of line for now
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*/
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switch_mmu_context(prev, next, tsk);
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}
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#ifndef CONFIG_PPC_BOOK3S_64
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void arch_exit_mmap(struct mm_struct *mm)
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{
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void *frag = pte_frag_get(&mm->context);
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if (frag)
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pte_frag_destroy(frag);
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}
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#endif
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