1509e93916
commit 950b879b7f0251317d26bae0687e72592d607532 upstream.
In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
in __sync_icache_dcache()"), we found RISC-V has the same issue as the
previous arm64. The previous implementation didn't guarantee the correct
sequence of operations, which means flush_icache_all() hasn't been
called when the PG_dcache_clean was set. That would cause a risk of page
synchronization.
Fixes: 08f051eda3
("RISC-V: Flush I$ when making a dirty page executable")
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230127035306.1819561-1-guoren@kernel.org
Cc: stable@vger.kernel.org
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
79 lines
2.1 KiB
C
79 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* Copyright (C) 2017 SiFive
|
|
*/
|
|
|
|
#include <asm/pgtable.h>
|
|
#include <asm/cacheflush.h>
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
#include <asm/sbi.h>
|
|
|
|
void flush_icache_all(void)
|
|
{
|
|
sbi_remote_fence_i(NULL);
|
|
}
|
|
EXPORT_SYMBOL(flush_icache_all);
|
|
|
|
/*
|
|
* Performs an icache flush for the given MM context. RISC-V has no direct
|
|
* mechanism for instruction cache shoot downs, so instead we send an IPI that
|
|
* informs the remote harts they need to flush their local instruction caches.
|
|
* To avoid pathologically slow behavior in a common case (a bunch of
|
|
* single-hart processes on a many-hart machine, ie 'make -j') we avoid the
|
|
* IPIs for harts that are not currently executing a MM context and instead
|
|
* schedule a deferred local instruction cache flush to be performed before
|
|
* execution resumes on each hart.
|
|
*/
|
|
void flush_icache_mm(struct mm_struct *mm, bool local)
|
|
{
|
|
unsigned int cpu;
|
|
cpumask_t others, hmask, *mask;
|
|
|
|
preempt_disable();
|
|
|
|
/* Mark every hart's icache as needing a flush for this MM. */
|
|
mask = &mm->context.icache_stale_mask;
|
|
cpumask_setall(mask);
|
|
/* Flush this hart's I$ now, and mark it as flushed. */
|
|
cpu = smp_processor_id();
|
|
cpumask_clear_cpu(cpu, mask);
|
|
local_flush_icache_all();
|
|
|
|
/*
|
|
* Flush the I$ of other harts concurrently executing, and mark them as
|
|
* flushed.
|
|
*/
|
|
cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
|
|
local |= cpumask_empty(&others);
|
|
if (mm != current->active_mm || !local) {
|
|
riscv_cpuid_to_hartid_mask(&others, &hmask);
|
|
sbi_remote_fence_i(hmask.bits);
|
|
} else {
|
|
/*
|
|
* It's assumed that at least one strongly ordered operation is
|
|
* performed on this hart between setting a hart's cpumask bit
|
|
* and scheduling this MM context on that hart. Sending an SBI
|
|
* remote message will do this, but in the case where no
|
|
* messages are sent we still need to order this hart's writes
|
|
* with flush_icache_deferred().
|
|
*/
|
|
smp_mb();
|
|
}
|
|
|
|
preempt_enable();
|
|
}
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
void flush_icache_pte(pte_t pte)
|
|
{
|
|
struct page *page = pte_page(pte);
|
|
|
|
if (!test_bit(PG_dcache_clean, &page->flags)) {
|
|
flush_icache_all();
|
|
set_bit(PG_dcache_clean, &page->flags);
|
|
}
|
|
}
|