b1511f7a48
- Support gated clk controller on MIPS based BCM63XX SoCs - Small frequency support for SiLabs Si544 chips - Support SiLabs Si5341 and Si5340 chips * clk-bcm63xx: clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings * clk-silabs: clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support * clk-lochnagar: clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: lochnagar: Use new parent_data approach to register clock parents * clk-rockchip: clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro clk: rockchip: add a type from SGRF-controlled gate clocks clk: rockchip: Remove 48 MHz PLL rate from rk3288 clk: rockchip: add 1.464GHz cpu-clock rate to rk3228 clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase() clk: rockchip: Don't yell about bad mmc phases when getting clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation
18 lines
788 B
Makefile
18 lines
788 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
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obj-$(CONFIG_CLK_BCM_63XX_GATE) += clk-bcm63xx-gate.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
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obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
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obj-$(CONFIG_CLK_BCM2835) += clk-bcm2835.o
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obj-$(CONFIG_CLK_BCM2835) += clk-bcm2835-aux.o
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obj-$(CONFIG_CLK_RASPBERRYPI) += clk-raspberrypi.o
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obj-$(CONFIG_ARCH_BCM_53573) += clk-bcm53573-ilp.o
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obj-$(CONFIG_CLK_BCM_CYGNUS) += clk-cygnus.o
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obj-$(CONFIG_CLK_BCM_HR2) += clk-hr2.o
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obj-$(CONFIG_CLK_BCM_NSP) += clk-nsp.o
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obj-$(CONFIG_CLK_BCM_NS2) += clk-ns2.o
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obj-$(CONFIG_CLK_BCM_SR) += clk-sr.o
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