d674cb90a9
commit 748c5ea8b8796ae8ee80b8d3a3d940570b588d59 upstream.
Preserve the original value of the Divisor Latch Fraction (DLF) register.
When the DLF register is modified without preservation, it can disrupt
the baudrate settings established by firmware or bootloader, leading to
data corruption and the generation of unreadable or distorted characters.
Fixes: 701c5e73b2 ("serial: 8250_dw: add fractional divisor support")
Cc: stable <stable@kernel.org>
Signed-off-by: Ruihong Luo <colorsu1922@gmail.com>
Link: https://lore.kernel.org/stable/20230713004235.35904-1-colorsu1922%40gmail.com
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20230713004235.35904-1-colorsu1922@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
129 lines
3.6 KiB
C
129 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Synopsys DesignWare 8250 library. */
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_core.h>
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#include "8250_dwlib.h"
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/* Offsets for the DesignWare specific registers */
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#define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */
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#define DW_UART_CPR 0xf4 /* Component Parameter Register */
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#define DW_UART_UCV 0xf8 /* UART Component Version */
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/* Component Parameter Register bits */
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#define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
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#define DW_UART_CPR_AFCE_MODE (1 << 4)
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#define DW_UART_CPR_THRE_MODE (1 << 5)
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#define DW_UART_CPR_SIR_MODE (1 << 6)
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#define DW_UART_CPR_SIR_LP_MODE (1 << 7)
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#define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
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#define DW_UART_CPR_FIFO_ACCESS (1 << 9)
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#define DW_UART_CPR_FIFO_STAT (1 << 10)
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#define DW_UART_CPR_SHADOW (1 << 11)
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#define DW_UART_CPR_ENCODED_PARMS (1 << 12)
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#define DW_UART_CPR_DMA_EXTRA (1 << 13)
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#define DW_UART_CPR_FIFO_MODE (0xff << 16)
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/* Helper for FIFO size calculation */
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#define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
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static inline u32 dw8250_readl_ext(struct uart_port *p, int offset)
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{
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if (p->iotype == UPIO_MEM32BE)
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return ioread32be(p->membase + offset);
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return readl(p->membase + offset);
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}
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static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg)
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{
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if (p->iotype == UPIO_MEM32BE)
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iowrite32be(reg, p->membase + offset);
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else
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writel(reg, p->membase + offset);
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}
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/*
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* divisor = div(I) + div(F)
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* "I" means integer, "F" means fractional
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* quot = div(I) = clk / (16 * baud)
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* frac = div(F) * 2^dlf_size
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*
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* let rem = clk % (16 * baud)
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* we have: div(F) * (16 * baud) = rem
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* so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud)
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*/
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static unsigned int dw8250_get_divisor(struct uart_port *p, unsigned int baud,
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unsigned int *frac)
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{
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unsigned int quot, rem, base_baud = baud * 16;
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struct dw8250_port_data *d = p->private_data;
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quot = p->uartclk / base_baud;
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rem = p->uartclk % base_baud;
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*frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud);
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return quot;
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}
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static void dw8250_set_divisor(struct uart_port *p, unsigned int baud,
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unsigned int quot, unsigned int quot_frac)
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{
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dw8250_writel_ext(p, DW_UART_DLF, quot_frac);
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serial8250_do_set_divisor(p, baud, quot, quot_frac);
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}
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void dw8250_setup_port(struct uart_port *p)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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u32 reg, old_dlf;
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/*
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* If the Component Version Register returns zero, we know that
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* ADDITIONAL_FEATURES are not enabled. No need to go any further.
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*/
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reg = dw8250_readl_ext(p, DW_UART_UCV);
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if (!reg)
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return;
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dev_dbg(p->dev, "Designware UART version %c.%c%c\n",
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(reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
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/* Preserve value written by firmware or bootloader */
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old_dlf = dw8250_readl_ext(p, DW_UART_DLF);
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dw8250_writel_ext(p, DW_UART_DLF, ~0U);
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reg = dw8250_readl_ext(p, DW_UART_DLF);
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dw8250_writel_ext(p, DW_UART_DLF, old_dlf);
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if (reg) {
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struct dw8250_port_data *d = p->private_data;
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d->dlf_size = fls(reg);
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p->get_divisor = dw8250_get_divisor;
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p->set_divisor = dw8250_set_divisor;
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}
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reg = dw8250_readl_ext(p, DW_UART_CPR);
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if (!reg)
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return;
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/* Select the type based on FIFO */
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if (reg & DW_UART_CPR_FIFO_MODE) {
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p->type = PORT_16550A;
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p->flags |= UPF_FIXED_TYPE;
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p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
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up->capabilities = UART_CAP_FIFO;
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}
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if (reg & DW_UART_CPR_AFCE_MODE)
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up->capabilities |= UART_CAP_AFE;
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if (reg & DW_UART_CPR_SIR_MODE)
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up->capabilities |= UART_CAP_IRDA;
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}
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EXPORT_SYMBOL_GPL(dw8250_setup_port);
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