b7a740512b
Add AMU counters interfaces for Arm cortex-A76, cortex-A77 and cortex-A78 CPUs. Change-Id: I81ae250fc5e1b2a2ffec904f4335f84f05543a83 Signed-off-by: Neeraj Upadhyay <neeraju@codeaurora.org>
128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#include <asm/cputype.h>
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#include <asm/sysreg.h>
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#include <linux/ratelimit.h>
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/* Definitions for system register interface to AMU for Cortex A76 and A77 CPUs */
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#define SYS_A76_AM_EL0(crm, op2) sys_reg(3, 3, 15, (crm), (op2))
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/*
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* Cortex A76 activity monitors:
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* op0 op1 CRn CRm op2
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* Counter: 11 011 1111 1001 n
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* Type: 11 011 1111 1010 n
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* n: 0-4
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*/
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#define SYS_A76_AMEVCNTR_EL0(n) SYS_A76_AM_EL0(9, (n))
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#define SYS_A76_AMEVTYPE_EL0(n) SYS_A76_AM_EL0(10, (n))
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/* Definitions for system register interface to AMU for Cortex A78 CPUs */
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#define SYS_A78_AM_EL0(crm, op2) sys_reg(3, 3, 15, (crm), (op2))
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/*
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* Cortex A78 Group 0 of activity monitors:
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* op0 op1 CRn CRm op2
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* Counter: 11 011 1111 100 n
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* Type: 11 011 1111 110 n
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* n: 0-3
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*
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* Cortex A78 Group 1 of activity monitors (auxiliary):
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* op0 op1 CRn CRm op2
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* Counter: 11 011 1111 1100 n
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* Type: 11 011 1111 1110 n
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* n: 0-2
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*/
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#define SYS_A78_AMEVCNTR0_EL0(n) SYS_A78_AM_EL0(4, (n))
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#define SYS_A78_AMEVTYPE0_EL0(n) SYS_A78_AM_EL0(6, (n))
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#define SYS_A78_AMEVCNTR1_EL0(n) SYS_A78_AM_EL0(12, (n))
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#define SYS_A78_AMEVTYPE1_EL0(n) SYS_A78_AM_EL0(14, (n))
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static u64 read_amevctr(int n)
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{
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u32 midr = read_cpuid_id();
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struct midr_range a76_midr_range = MIDR_ALL_VERSIONS(MIDR_CORTEX_A76);
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struct midr_range a77_midr_range = MIDR_ALL_VERSIONS(MIDR_CORTEX_A77);
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struct midr_range a78_midr_range = MIDR_ALL_VERSIONS(MIDR_CORTEX_A78);
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struct midr_range kryo_4g_midr_range = MIDR_ALL_VERSIONS(MIDR_KRYO4G);
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WARN_ON(preemptible());
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if (n < 0 || n > 4) {
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pr_err("%s Invalid counter ID: %d\n", __func__, n);
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return 0;
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}
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if (is_midr_in_range(midr, &a76_midr_range) ||
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is_midr_in_range(midr, &a77_midr_range) ||
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is_midr_in_range(midr, &kryo_4g_midr_range)) {
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switch (n) {
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case 0:
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return read_sysreg_s(SYS_A76_AMEVCNTR_EL0(0));
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case 1:
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return read_sysreg_s(SYS_A76_AMEVCNTR_EL0(1));
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case 2:
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return read_sysreg_s(SYS_A76_AMEVCNTR_EL0(2));
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case 3:
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return read_sysreg_s(SYS_A76_AMEVCNTR_EL0(3));
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case 4:
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return read_sysreg_s(SYS_A76_AMEVCNTR_EL0(4));
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default:
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pr_err("%s Invalid counter ID: %d\n", __func__, n);
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return 0;
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}
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}
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if (is_midr_in_range(midr, &a78_midr_range)) {
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switch (n) {
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case 0:
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return read_sysreg_s(SYS_A78_AMEVCNTR0_EL0(0));
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case 1:
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return read_sysreg_s(SYS_A78_AMEVCNTR0_EL0(1));
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case 2:
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return read_sysreg_s(SYS_A78_AMEVCNTR0_EL0(2));
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case 3:
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return read_sysreg_s(SYS_A78_AMEVCNTR0_EL0(3));
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default:
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pr_err("%s Invalid counter ID: %d\n", __func__, n);
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return 0;
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}
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}
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return 0;
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}
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/* Core frequency cycles */
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static u64 __maybe_unused read_amevctr_core(void)
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{
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return read_amevctr(0);
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}
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/* Const frequency cycles */
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static u64 __maybe_unused read_amevctr_const(void)
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{
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return read_amevctr(1);
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}
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/* Instructions retired */
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static u64 __maybe_unused read_amevctr_instret(void)
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{
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return read_amevctr(2);
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}
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/* Memory stall cycles */
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static u64 __maybe_unused read_amevctr_memstall(void)
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{
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return read_amevctr(3);
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}
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/* High activity */
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static u64 __maybe_unused read_amevctr_highact(void)
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{
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return read_amevctr(4);
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}
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