780a156888
This updates the SH7619 and SH7206 code for the IPR IRQ changes. Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
148 lines
3.0 KiB
C
148 lines
3.0 KiB
C
/*
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* linux/arch/sh/boards/se/7206/irq.c
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*
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* Copyright (C) 2005,2006 Yoshinori Sato
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*
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* Hitachi SolutionEngine Support.
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*
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <asm/se7206.h>
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#define INTSTS0 0x31800000
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#define INTSTS1 0x31800002
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#define INTMSK0 0x31800004
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#define INTMSK1 0x31800006
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#define INTSEL 0x31800008
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#define IRQ0_IRQ 64
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#define IRQ1_IRQ 65
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#define IRQ3_IRQ 67
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#define INTC_IPR01 0xfffe0818
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#define INTC_ICR1 0xfffe0802
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static void disable_se7206_irq(unsigned int irq)
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{
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unsigned short val;
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unsigned short mask = 0xffff ^ (0x0f << 4 * (3 - (IRQ0_IRQ - irq)));
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unsigned short msk0,msk1;
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/* Set the priority in IPR to 0 */
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val = ctrl_inw(INTC_IPR01);
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val &= mask;
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ctrl_outw(val, INTC_IPR01);
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/* FPGA mask set */
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msk0 = ctrl_inw(INTMSK0);
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msk1 = ctrl_inw(INTMSK1);
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switch (irq) {
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case IRQ0_IRQ:
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msk0 |= 0x0010;
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break;
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case IRQ1_IRQ:
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msk0 |= 0x000f;
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break;
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case IRQ3_IRQ:
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msk0 |= 0x0f00;
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msk1 |= 0x00ff;
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break;
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}
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ctrl_outw(msk0, INTMSK0);
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ctrl_outw(msk1, INTMSK1);
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}
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static void enable_se7206_irq(unsigned int irq)
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{
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unsigned short val;
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unsigned short value = (0x0001 << 4 * (3 - (IRQ0_IRQ - irq)));
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unsigned short msk0,msk1;
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/* Set priority in IPR back to original value */
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val = ctrl_inw(INTC_IPR01);
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val |= value;
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ctrl_outw(val, INTC_IPR01);
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/* FPGA mask reset */
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msk0 = ctrl_inw(INTMSK0);
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msk1 = ctrl_inw(INTMSK1);
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switch (irq) {
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case IRQ0_IRQ:
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msk0 &= ~0x0010;
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break;
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case IRQ1_IRQ:
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msk0 &= ~0x000f;
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break;
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case IRQ3_IRQ:
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msk0 &= ~0x0f00;
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msk1 &= ~0x00ff;
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break;
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}
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ctrl_outw(msk0, INTMSK0);
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ctrl_outw(msk1, INTMSK1);
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}
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static void eoi_se7206_irq(unsigned int irq)
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{
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unsigned short sts0,sts1;
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
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enable_se7206_irq(irq);
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/* FPGA isr clear */
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sts0 = ctrl_inw(INTSTS0);
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sts1 = ctrl_inw(INTSTS1);
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switch (irq) {
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case IRQ0_IRQ:
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sts0 &= ~0x0010;
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break;
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case IRQ1_IRQ:
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sts0 &= ~0x000f;
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break;
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case IRQ3_IRQ:
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sts0 &= ~0x0f00;
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sts1 &= ~0x00ff;
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break;
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}
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ctrl_outw(sts0, INTSTS0);
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ctrl_outw(sts1, INTSTS1);
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}
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static struct irq_chip se7206_irq_chip __read_mostly = {
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.name = "SE7206-FPGA",
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.mask = disable_se7206_irq,
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.unmask = enable_se7206_irq,
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.mask_ack = disable_se7206_irq,
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.eoi = eoi_se7206_irq,
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};
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static void make_se7206_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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set_irq_chip_and_handler_name(irq, &se7206_irq_chip,
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handle_level_irq, "level");
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disable_se7206_irq(irq);
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}
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/*
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* Initialize IRQ setting
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*/
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void __init init_se7206_IRQ(void)
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{
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make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
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make_se7206_irq(IRQ1_IRQ); /* ATA */
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make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
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ctrl_outw(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
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/* FPGA System register setup*/
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ctrl_outw(0x0000,INTSTS0); /* Clear INTSTS0 */
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ctrl_outw(0x0000,INTSTS1); /* Clear INTSTS1 */
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/* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
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ctrl_outw(0x0001,INTSEL);
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}
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