a27fe809b8
Back out the map_pt_hook to clear the way for kmap_atomic_pte. Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com> Signed-off-by: Andi Kleen <ak@suse.de> Cc: Zachary Amsden <zach@vmware.com>
536 lines
18 KiB
C
536 lines
18 KiB
C
#ifndef _I386_PGTABLE_H
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#define _I386_PGTABLE_H
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/*
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* The Linux memory management assumes a three-level page table setup. On
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* the i386, we use that, but "fold" the mid level into the top-level page
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* table, so that we physically have the same two-level page table as the
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* i386 mmu expects.
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*
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* This file contains the functions and defines necessary to modify and use
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* the i386 page table tree.
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*/
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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#include <asm/fixmap.h>
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#include <linux/threads.h>
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#include <asm/paravirt.h>
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#ifndef _I386_BITOPS_H
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#include <asm/bitops.h>
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#endif
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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struct mm_struct;
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struct vm_area_struct;
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/*
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* ZERO_PAGE is a global shared page that is always zero: used
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* for zero-mapped memory areas etc..
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*/
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern unsigned long empty_zero_page[1024];
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extern pgd_t swapper_pg_dir[1024];
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extern struct kmem_cache *pgd_cache;
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extern struct kmem_cache *pmd_cache;
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extern spinlock_t pgd_lock;
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extern struct page *pgd_list;
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void pmd_ctor(void *, struct kmem_cache *, unsigned long);
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void pgd_ctor(void *, struct kmem_cache *, unsigned long);
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void pgd_dtor(void *, struct kmem_cache *, unsigned long);
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void pgtable_cache_init(void);
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void paging_init(void);
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/*
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* The Linux x86 paging architecture is 'compile-time dual-mode', it
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* implements both the traditional 2-level x86 page tables and the
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* newer 3-level PAE-mode page tables.
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*/
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#ifdef CONFIG_X86_PAE
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# include <asm/pgtable-3level-defs.h>
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# define PMD_SIZE (1UL << PMD_SHIFT)
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# define PMD_MASK (~(PMD_SIZE-1))
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#else
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# include <asm/pgtable-2level-defs.h>
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#endif
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#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK (~(PGDIR_SIZE-1))
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#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_ADDRESS 0
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#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
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#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
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#define TWOLEVEL_PGDIR_SHIFT 22
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#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
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#define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
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/* Just any arbitrary offset to the start of the vmalloc VM area: the
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* current 8MB value just means that there will be a 8MB "hole" after the
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* physical memory until the kernel virtual memory starts. That means that
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* any out-of-bounds memory accesses will hopefully be caught.
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* The vmalloc() routines leaves a hole of 4kB between each vmalloced
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* area for the same reason. ;)
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*/
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#define VMALLOC_OFFSET (8*1024*1024)
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#define VMALLOC_START (((unsigned long) high_memory + vmalloc_earlyreserve + \
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2*VMALLOC_OFFSET-1) & ~(VMALLOC_OFFSET-1))
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#ifdef CONFIG_HIGHMEM
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# define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
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#else
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# define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
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#endif
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/*
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* _PAGE_PSE set in the page directory entry just means that
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* the page directory entry points directly to a 4MB-aligned block of
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* memory.
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*/
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#define _PAGE_BIT_PRESENT 0
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#define _PAGE_BIT_RW 1
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#define _PAGE_BIT_USER 2
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#define _PAGE_BIT_PWT 3
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#define _PAGE_BIT_PCD 4
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#define _PAGE_BIT_ACCESSED 5
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#define _PAGE_BIT_DIRTY 6
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#define _PAGE_BIT_PSE 7 /* 4 MB (or 2MB) page, Pentium+, if present.. */
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#define _PAGE_BIT_GLOBAL 8 /* Global TLB entry PPro+ */
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#define _PAGE_BIT_UNUSED1 9 /* available for programmer */
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#define _PAGE_BIT_UNUSED2 10
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#define _PAGE_BIT_UNUSED3 11
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#define _PAGE_BIT_NX 63
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#define _PAGE_PRESENT 0x001
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#define _PAGE_RW 0x002
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#define _PAGE_USER 0x004
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#define _PAGE_PWT 0x008
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#define _PAGE_PCD 0x010
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#define _PAGE_ACCESSED 0x020
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#define _PAGE_DIRTY 0x040
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#define _PAGE_PSE 0x080 /* 4 MB (or 2MB) page, Pentium+, if present.. */
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#define _PAGE_GLOBAL 0x100 /* Global TLB entry PPro+ */
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#define _PAGE_UNUSED1 0x200 /* available for programmer */
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#define _PAGE_UNUSED2 0x400
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#define _PAGE_UNUSED3 0x800
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/* If _PAGE_PRESENT is clear, we use these: */
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#define _PAGE_FILE 0x040 /* nonlinear file mapping, saved PTE; unset:swap */
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#define _PAGE_PROTNONE 0x080 /* if the user mapped it with PROT_NONE;
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pte_present gives true */
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#ifdef CONFIG_X86_PAE
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#define _PAGE_NX (1ULL<<_PAGE_BIT_NX)
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#else
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#define _PAGE_NX 0
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#endif
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#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define PAGE_NONE \
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__pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
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#define PAGE_SHARED \
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__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
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#define PAGE_SHARED_EXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
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#define PAGE_COPY_NOEXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
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#define PAGE_COPY_EXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
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#define PAGE_COPY \
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PAGE_COPY_NOEXEC
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#define PAGE_READONLY \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_NX)
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#define PAGE_READONLY_EXEC \
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__pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
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#define _PAGE_KERNEL \
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(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_NX)
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#define _PAGE_KERNEL_EXEC \
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(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
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extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
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#define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
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#define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW)
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#define __PAGE_KERNEL_NOCACHE (__PAGE_KERNEL | _PAGE_PCD)
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#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
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#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
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#define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
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#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
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#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
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#define PAGE_KERNEL_RX __pgprot(__PAGE_KERNEL_RX)
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#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
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#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
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#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
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/*
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* The i386 can't do page protection for execute, and considers that
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* the same are read. Also, write permissions imply read permissions.
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* This is the closest we can get..
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*/
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#define __P000 PAGE_NONE
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#define __P001 PAGE_READONLY
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#define __P010 PAGE_COPY
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#define __P011 PAGE_COPY
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#define __P100 PAGE_READONLY_EXEC
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#define __P101 PAGE_READONLY_EXEC
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#define __P110 PAGE_COPY_EXEC
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#define __P111 PAGE_COPY_EXEC
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#define __S000 PAGE_NONE
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#define __S001 PAGE_READONLY
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#define __S010 PAGE_SHARED
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#define __S011 PAGE_SHARED
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#define __S100 PAGE_READONLY_EXEC
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#define __S101 PAGE_READONLY_EXEC
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#define __S110 PAGE_SHARED_EXEC
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#define __S111 PAGE_SHARED_EXEC
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/*
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* Define this if things work differently on an i386 and an i486:
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* it will (on an i486) warn about kernel memory accesses that are
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* done without a 'access_ok(VERIFY_WRITE,..)'
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*/
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#undef TEST_ACCESS_OK
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/* The boot page tables (all created as a single array) */
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extern unsigned long pg0[];
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#define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
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/* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
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#define pmd_none(x) (!(unsigned long)pmd_val(x))
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#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
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#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
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#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
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/*
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* The following only work if pte_present() is true.
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* Undefined behaviour if not..
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*/
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static inline int pte_user(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
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static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_USER; }
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static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_DIRTY; }
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static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
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static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_RW; }
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static inline int pte_huge(pte_t pte) { return (pte).pte_low & _PAGE_PSE; }
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/*
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* The following only works if pte_present() is not true.
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*/
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static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; }
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static inline pte_t pte_rdprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
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static inline pte_t pte_exprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_USER; return pte; }
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static inline pte_t pte_mkclean(pte_t pte) { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkold(pte_t pte) { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
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static inline pte_t pte_wrprotect(pte_t pte) { (pte).pte_low &= ~_PAGE_RW; return pte; }
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static inline pte_t pte_mkread(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
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static inline pte_t pte_mkexec(pte_t pte) { (pte).pte_low |= _PAGE_USER; return pte; }
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static inline pte_t pte_mkdirty(pte_t pte) { (pte).pte_low |= _PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkyoung(pte_t pte) { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
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static inline pte_t pte_mkwrite(pte_t pte) { (pte).pte_low |= _PAGE_RW; return pte; }
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static inline pte_t pte_mkhuge(pte_t pte) { (pte).pte_low |= _PAGE_PSE; return pte; }
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extern void vmalloc_sync_all(void);
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#ifdef CONFIG_X86_PAE
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# include <asm/pgtable-3level.h>
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#else
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# include <asm/pgtable-2level.h>
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#endif
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#ifndef CONFIG_PARAVIRT
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/*
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* Rules for using pte_update - it must be called after any PTE update which
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* has not been done using the set_pte / clear_pte interfaces. It is used by
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* shadow mode hypervisors to resynchronize the shadow page tables. Kernel PTE
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* updates should either be sets, clears, or set_pte_atomic for P->P
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* transitions, which means this hook should only be called for user PTEs.
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* This hook implies a P->P protection or access change has taken place, which
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* requires a subsequent TLB flush. The notification can optionally be delayed
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* until the TLB flush event by using the pte_update_defer form of the
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* interface, but care must be taken to assure that the flush happens while
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* still holding the same page table lock so that the shadow and primary pages
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* do not become out of sync on SMP.
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*/
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#define pte_update(mm, addr, ptep) do { } while (0)
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#define pte_update_defer(mm, addr, ptep) do { } while (0)
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#define raw_ptep_get_and_clear(xp) native_ptep_get_and_clear(xp)
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#endif
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/*
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* We only update the dirty/accessed state if we set
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* the dirty bit by hand in the kernel, since the hardware
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* will do the accessed bit for us, and we don't want to
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* race with other CPU's that might be updating the dirty
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* bit at the same time.
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*/
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#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
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#define ptep_set_access_flags(vma, address, ptep, entry, dirty) \
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do { \
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if (dirty) { \
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(ptep)->pte_low = (entry).pte_low; \
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pte_update_defer((vma)->vm_mm, (address), (ptep)); \
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flush_tlb_page(vma, address); \
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} \
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} while (0)
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/*
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* We don't actually have these, but we want to advertise them so that
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* we can encompass the flush here.
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*/
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
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#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
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/*
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* Rules for using ptep_establish: the pte MUST be a user pte, and
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* must be a present->present transition.
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*/
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#define __HAVE_ARCH_PTEP_ESTABLISH
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#define ptep_establish(vma, address, ptep, pteval) \
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do { \
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set_pte_present((vma)->vm_mm, address, ptep, pteval); \
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flush_tlb_page(vma, address); \
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} while (0)
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#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
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#define ptep_clear_flush_dirty(vma, address, ptep) \
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({ \
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int __dirty; \
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__dirty = pte_dirty(*(ptep)); \
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if (__dirty) { \
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clear_bit(_PAGE_BIT_DIRTY, &(ptep)->pte_low); \
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pte_update_defer((vma)->vm_mm, (address), (ptep)); \
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flush_tlb_page(vma, address); \
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} \
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__dirty; \
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})
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#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
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#define ptep_clear_flush_young(vma, address, ptep) \
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({ \
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int __young; \
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__young = pte_young(*(ptep)); \
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if (__young) { \
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clear_bit(_PAGE_BIT_ACCESSED, &(ptep)->pte_low); \
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pte_update_defer((vma)->vm_mm, (address), (ptep)); \
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flush_tlb_page(vma, address); \
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} \
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__young; \
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})
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
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static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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pte_t pte = raw_ptep_get_and_clear(ptep);
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pte_update(mm, addr, ptep);
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return pte;
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}
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#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
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static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long addr, pte_t *ptep, int full)
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{
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pte_t pte;
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if (full) {
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pte = *ptep;
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pte_clear(mm, addr, ptep);
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} else {
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pte = ptep_get_and_clear(mm, addr, ptep);
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}
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return pte;
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}
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#define __HAVE_ARCH_PTEP_SET_WRPROTECT
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static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
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{
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clear_bit(_PAGE_BIT_RW, &ptep->pte_low);
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pte_update(mm, addr, ptep);
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}
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/*
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* clone_pgd_range(pgd_t *dst, pgd_t *src, int count);
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*
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* dst - pointer to pgd range anwhere on a pgd page
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* src - ""
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* count - the number of pgds to copy.
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*
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* dst and src can be on the same page, but the range must not overlap,
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* and must not cross a page boundary.
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*/
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static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
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{
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memcpy(dst, src, count * sizeof(pgd_t));
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}
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/*
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* Macro to mark a page protection value as "uncacheable". On processors which do not support
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* it, this is a no-op.
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*/
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#define pgprot_noncached(prot) ((boot_cpu_data.x86 > 3) \
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? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot))
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
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static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
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{
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pte.pte_low &= _PAGE_CHG_MASK;
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pte.pte_low |= pgprot_val(newprot);
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#ifdef CONFIG_X86_PAE
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/*
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* Chop off the NX bit (if present), and add the NX portion of
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* the newprot (if present):
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*/
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pte.pte_high &= ~(1 << (_PAGE_BIT_NX - 32));
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pte.pte_high |= (pgprot_val(newprot) >> 32) & \
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(__supported_pte_mask >> 32);
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#endif
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return pte;
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}
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#define pmd_large(pmd) \
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((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
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/*
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* the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
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*
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* this macro returns the index of the entry in the pgd page which would
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* control the given virtual address
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*/
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#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
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#define pgd_index_k(addr) pgd_index(addr)
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/*
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* pgd_offset() returns a (pgd_t *)
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* pgd_index() is used get the offset into the pgd page's array of pgd_t's;
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*/
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#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
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/*
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* a shortcut which implies the use of the kernel's pgd, instead
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* of a process's
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*/
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#define pgd_offset_k(address) pgd_offset(&init_mm, address)
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/*
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* the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
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*
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* this macro returns the index of the entry in the pmd page which would
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* control the given virtual address
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*/
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#define pmd_index(address) \
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(((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
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/*
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* the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
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*
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* this macro returns the index of the entry in the pte page which would
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* control the given virtual address
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*/
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#define pte_index(address) \
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(((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
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#define pte_offset_kernel(dir, address) \
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((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(address))
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#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
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#define pmd_page_vaddr(pmd) \
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((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
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/*
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* Helper function that returns the kernel pagetable entry controlling
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* the virtual address 'address'. NULL means no pagetable entry present.
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* NOTE: the return type is pte_t but if the pmd is PSE then we return it
|
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* as a pte too.
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|
*/
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extern pte_t *lookup_address(unsigned long address);
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|
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/*
|
|
* Make a given kernel text page executable/non-executable.
|
|
* Returns the previous executability setting of that page (which
|
|
* is used to restore the previous state). Used by the SMP bootup code.
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|
* NOTE: this is an __init function for security reasons.
|
|
*/
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|
#ifdef CONFIG_X86_PAE
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|
extern int set_kernel_exec(unsigned long vaddr, int enable);
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#else
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static inline int set_kernel_exec(unsigned long vaddr, int enable) { return 0;}
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|
#endif
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|
|
#if defined(CONFIG_HIGHPTE)
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|
#define pte_offset_map(dir, address) \
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((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE0) + pte_index(address))
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|
#define pte_offset_map_nested(dir, address) \
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|
((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE1) + pte_index(address))
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|
#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
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|
#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
|
|
#else
|
|
#define pte_offset_map(dir, address) \
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|
((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
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|
#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
|
|
#define pte_unmap(pte) do { } while (0)
|
|
#define pte_unmap_nested(pte) do { } while (0)
|
|
#endif
|
|
|
|
/* Clear a kernel PTE and flush it from the TLB */
|
|
#define kpte_clear_flush(ptep, vaddr) \
|
|
do { \
|
|
pte_clear(&init_mm, vaddr, ptep); \
|
|
__flush_tlb_one(vaddr); \
|
|
} while (0)
|
|
|
|
/*
|
|
* The i386 doesn't have any external MMU info: the kernel page
|
|
* tables contain all the necessary information.
|
|
*/
|
|
#define update_mmu_cache(vma,address,pte) do { } while (0)
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|
|
|
void native_pagetable_setup_start(pgd_t *base);
|
|
void native_pagetable_setup_done(pgd_t *base);
|
|
|
|
#ifndef CONFIG_PARAVIRT
|
|
static inline void paravirt_pagetable_setup_start(pgd_t *base)
|
|
{
|
|
native_pagetable_setup_start(base);
|
|
}
|
|
|
|
static inline void paravirt_pagetable_setup_done(pgd_t *base)
|
|
{
|
|
native_pagetable_setup_done(base);
|
|
}
|
|
#endif /* !CONFIG_PARAVIRT */
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
#ifdef CONFIG_FLATMEM
|
|
#define kern_addr_valid(addr) (1)
|
|
#endif /* CONFIG_FLATMEM */
|
|
|
|
#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
|
|
remap_pfn_range(vma, vaddr, pfn, size, prot)
|
|
|
|
#define MK_IOSPACE_PFN(space, pfn) (pfn)
|
|
#define GET_IOSPACE(pfn) 0
|
|
#define GET_PFN(pfn) (pfn)
|
|
|
|
#include <asm-generic/pgtable.h>
|
|
|
|
#endif /* _I386_PGTABLE_H */
|