1cb68487f5
Indicate TSCs are unreliable as time sources if the platform is a multi chassi ScaleMP vSMPowered machine. Signed-off-by: Ravikiran Thirumalai <kiran@scalex86.org> Signed-off-by: Ingo Molnar <mingo@elte.hu>
1347 lines
32 KiB
C
1347 lines
32 KiB
C
/*
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* Local APIC handling, local APIC timers
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*
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* (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
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*
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* Fixes
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* Maciej W. Rozycki : Bits for genuine 82489DX APICs;
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* thanks to Eric Gilmore
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* and Rolf G. Tews
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* for testing these extensively.
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* Maciej W. Rozycki : Various updates and fixes.
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* Mikael Pettersson : Power Management for UP-APIC.
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* Pavel Machek and
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* Mikael Pettersson : PM converted to driver model.
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*/
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/bootmem.h>
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#include <linux/interrupt.h>
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#include <linux/mc146818rtc.h>
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#include <linux/kernel_stat.h>
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#include <linux/sysdev.h>
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#include <linux/ioport.h>
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#include <linux/clockchips.h>
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#include <linux/acpi_pmtmr.h>
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#include <linux/module.h>
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#include <asm/atomic.h>
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#include <asm/smp.h>
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#include <asm/mtrr.h>
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#include <asm/mpspec.h>
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#include <asm/hpet.h>
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#include <asm/pgalloc.h>
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#include <asm/mach_apic.h>
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#include <asm/nmi.h>
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#include <asm/idle.h>
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#include <asm/proto.h>
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#include <asm/timex.h>
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#include <asm/apic.h>
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int disable_apic_timer __cpuinitdata;
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static int apic_calibrate_pmtmr __initdata;
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int disable_apic;
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/* Local APIC timer works in C2 */
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int local_apic_timer_c2_ok;
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EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
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/*
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* Debug level, exported for io_apic.c
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*/
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int apic_verbosity;
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static struct resource lapic_resource = {
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.name = "Local APIC",
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.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
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};
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static unsigned int calibration_result;
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static int lapic_next_event(unsigned long delta,
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struct clock_event_device *evt);
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static void lapic_timer_setup(enum clock_event_mode mode,
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struct clock_event_device *evt);
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static void lapic_timer_broadcast(cpumask_t mask);
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static void apic_pm_activate(void);
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static struct clock_event_device lapic_clockevent = {
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.name = "lapic",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
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| CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
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.shift = 32,
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.set_mode = lapic_timer_setup,
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.set_next_event = lapic_next_event,
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.broadcast = lapic_timer_broadcast,
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.rating = 100,
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.irq = -1,
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};
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static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
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static unsigned long apic_phys;
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/*
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* Get the LAPIC version
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*/
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static inline int lapic_get_version(void)
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{
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return GET_APIC_VERSION(apic_read(APIC_LVR));
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}
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/*
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* Check, if the APIC is integrated or a seperate chip
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*/
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static inline int lapic_is_integrated(void)
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{
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return 1;
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}
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/*
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* Check, whether this is a modern or a first generation APIC
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*/
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static int modern_apic(void)
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{
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/* AMD systems use old APIC versions, so check the CPU */
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if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
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boot_cpu_data.x86 >= 0xf)
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return 1;
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return lapic_get_version() >= 0x14;
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}
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void apic_wait_icr_idle(void)
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{
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while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
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cpu_relax();
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}
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u32 safe_apic_wait_icr_idle(void)
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{
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u32 send_status;
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int timeout;
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timeout = 0;
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do {
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send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
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if (!send_status)
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break;
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udelay(100);
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} while (timeout++ < 1000);
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return send_status;
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}
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/**
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* enable_NMI_through_LVT0 - enable NMI through local vector table 0
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*/
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void __cpuinit enable_NMI_through_LVT0(void)
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{
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unsigned int v;
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/* unmask and set to NMI */
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v = APIC_DM_NMI;
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apic_write(APIC_LVT0, v);
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}
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/**
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* lapic_get_maxlvt - get the maximum number of local vector table entries
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*/
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int lapic_get_maxlvt(void)
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{
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unsigned int v, maxlvt;
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v = apic_read(APIC_LVR);
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maxlvt = GET_APIC_MAXLVT(v);
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return maxlvt;
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}
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/*
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* This function sets up the local APIC timer, with a timeout of
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* 'clocks' APIC bus clock. During calibration we actually call
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* this function twice on the boot CPU, once with a bogus timeout
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* value, second time for real. The other (noncalibrating) CPUs
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* call this function only once, with the real, calibrated value.
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*
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* We do reads before writes even if unnecessary, to get around the
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* P5 APIC double write bug.
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*/
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static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
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{
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unsigned int lvtt_value, tmp_value;
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lvtt_value = LOCAL_TIMER_VECTOR;
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if (!oneshot)
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lvtt_value |= APIC_LVT_TIMER_PERIODIC;
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if (!irqen)
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lvtt_value |= APIC_LVT_MASKED;
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apic_write(APIC_LVTT, lvtt_value);
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/*
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* Divide PICLK by 16
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*/
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tmp_value = apic_read(APIC_TDCR);
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apic_write(APIC_TDCR, (tmp_value
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& ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
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| APIC_TDR_DIV_16);
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if (!oneshot)
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apic_write(APIC_TMICT, clocks);
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}
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/*
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* Setup extended LVT, AMD specific (K8, family 10h)
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*
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* Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
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* MCE interrupts are supported. Thus MCE offset must be set to 0.
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*/
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#define APIC_EILVT_LVTOFF_MCE 0
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#define APIC_EILVT_LVTOFF_IBS 1
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static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
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{
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unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
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unsigned int v = (mask << 16) | (msg_type << 8) | vector;
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apic_write(reg, v);
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}
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u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
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{
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setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
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return APIC_EILVT_LVTOFF_MCE;
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}
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u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
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{
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setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
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return APIC_EILVT_LVTOFF_IBS;
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}
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/*
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* Program the next event, relative to now
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*/
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static int lapic_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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apic_write(APIC_TMICT, delta);
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return 0;
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}
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/*
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* Setup the lapic timer in periodic or oneshot mode
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*/
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static void lapic_timer_setup(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long flags;
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unsigned int v;
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/* Lapic used as dummy for broadcast ? */
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if (evt->features & CLOCK_EVT_FEAT_DUMMY)
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return;
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local_irq_save(flags);
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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case CLOCK_EVT_MODE_ONESHOT:
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__setup_APIC_LVTT(calibration_result,
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mode != CLOCK_EVT_MODE_PERIODIC, 1);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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v = apic_read(APIC_LVTT);
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v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
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apic_write(APIC_LVTT, v);
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break;
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case CLOCK_EVT_MODE_RESUME:
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/* Nothing to do here */
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break;
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}
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local_irq_restore(flags);
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}
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/*
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* Local APIC timer broadcast function
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*/
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static void lapic_timer_broadcast(cpumask_t mask)
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{
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#ifdef CONFIG_SMP
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send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
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#endif
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}
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/*
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* Setup the local APIC timer for this CPU. Copy the initilized values
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* of the boot CPU and register the clock event in the framework.
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*/
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static void setup_APIC_timer(void)
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{
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struct clock_event_device *levt = &__get_cpu_var(lapic_events);
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memcpy(levt, &lapic_clockevent, sizeof(*levt));
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levt->cpumask = cpumask_of_cpu(smp_processor_id());
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clockevents_register_device(levt);
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}
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/*
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* In this function we calibrate APIC bus clocks to the external
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* timer. Unfortunately we cannot use jiffies and the timer irq
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* to calibrate, since some later bootup code depends on getting
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* the first irq? Ugh.
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*
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* We want to do the calibration only once since we
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* want to have local timer irqs syncron. CPUs connected
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* by the same APIC bus have the very same bus frequency.
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* And we want to have irqs off anyways, no accidental
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* APIC irq that way.
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*/
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#define TICK_COUNT 100000000
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static void __init calibrate_APIC_clock(void)
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{
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unsigned apic, apic_start;
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unsigned long tsc, tsc_start;
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int result;
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local_irq_disable();
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/*
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* Put whatever arbitrary (but long enough) timeout
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* value into the APIC clock, we just want to get the
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* counter running for calibration.
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*
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* No interrupt enable !
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*/
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__setup_APIC_LVTT(250000000, 0, 0);
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apic_start = apic_read(APIC_TMCCT);
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#ifdef CONFIG_X86_PM_TIMER
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if (apic_calibrate_pmtmr && pmtmr_ioport) {
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pmtimer_wait(5000); /* 5ms wait */
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apic = apic_read(APIC_TMCCT);
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result = (apic_start - apic) * 1000L / 5;
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} else
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#endif
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{
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rdtscll(tsc_start);
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do {
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apic = apic_read(APIC_TMCCT);
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rdtscll(tsc);
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} while ((tsc - tsc_start) < TICK_COUNT &&
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(apic_start - apic) < TICK_COUNT);
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result = (apic_start - apic) * 1000L * tsc_khz /
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(tsc - tsc_start);
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}
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local_irq_enable();
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printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
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printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
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result / 1000 / 1000, result / 1000 % 1000);
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/* Calculate the scaled math multiplication factor */
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lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC, 32);
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lapic_clockevent.max_delta_ns =
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clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
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lapic_clockevent.min_delta_ns =
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clockevent_delta2ns(0xF, &lapic_clockevent);
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calibration_result = result / HZ;
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}
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/*
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* Setup the boot APIC
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*
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* Calibrate and verify the result.
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*/
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void __init setup_boot_APIC_clock(void)
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{
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/*
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* The local apic timer can be disabled via the kernel commandline.
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* Register the lapic timer as a dummy clock event source on SMP
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* systems, so the broadcast mechanism is used. On UP systems simply
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* ignore it.
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*/
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if (disable_apic_timer) {
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printk(KERN_INFO "Disabling APIC timer\n");
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/* No broadcast on UP ! */
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if (num_possible_cpus() > 1) {
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lapic_clockevent.mult = 1;
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setup_APIC_timer();
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}
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return;
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}
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printk(KERN_INFO "Using local APIC timer interrupts.\n");
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calibrate_APIC_clock();
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/*
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* Do a sanity check on the APIC calibration result
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*/
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if (calibration_result < (1000000 / HZ)) {
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printk(KERN_WARNING
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"APIC frequency too slow, disabling apic timer\n");
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/* No broadcast on UP ! */
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if (num_possible_cpus() > 1)
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setup_APIC_timer();
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return;
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}
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/*
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* If nmi_watchdog is set to IO_APIC, we need the
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* PIT/HPET going. Otherwise register lapic as a dummy
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* device.
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*/
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if (nmi_watchdog != NMI_IO_APIC)
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lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
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else
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printk(KERN_WARNING "APIC timer registered as dummy,"
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" due to nmi_watchdog=1!\n");
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setup_APIC_timer();
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}
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/*
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* AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
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* C1E flag only in the secondary CPU, so when we detect the wreckage
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* we already have enabled the boot CPU local apic timer. Check, if
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* disable_apic_timer is set and the DUMMY flag is cleared. If yes,
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* set the DUMMY flag again and force the broadcast mode in the
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* clockevents layer.
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*/
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void __cpuinit check_boot_apic_timer_broadcast(void)
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{
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if (!disable_apic_timer ||
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(lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
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return;
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printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
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lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
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local_irq_enable();
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clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
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&boot_cpu_physical_apicid);
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local_irq_disable();
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}
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void __cpuinit setup_secondary_APIC_clock(void)
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{
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check_boot_apic_timer_broadcast();
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setup_APIC_timer();
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}
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/*
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* The guts of the apic timer interrupt
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*/
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static void local_apic_timer_interrupt(void)
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{
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int cpu = smp_processor_id();
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struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
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/*
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* Normally we should not be here till LAPIC has been initialized but
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* in some cases like kdump, its possible that there is a pending LAPIC
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* timer interrupt from previous kernel's context and is delivered in
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* new kernel the moment interrupts are enabled.
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*
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* Interrupts are enabled early and LAPIC is setup much later, hence
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* its possible that when we get here evt->event_handler is NULL.
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* Check for event_handler being NULL and discard the interrupt as
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* spurious.
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*/
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if (!evt->event_handler) {
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printk(KERN_WARNING
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"Spurious LAPIC timer interrupt on cpu %d\n", cpu);
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/* Switch it off */
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lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
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return;
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}
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/*
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* the NMI deadlock-detector uses this.
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*/
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add_pda(apic_timer_irqs, 1);
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evt->event_handler(evt);
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}
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/*
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* Local APIC timer interrupt. This is the most natural way for doing
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* local interrupts, but local timer interrupts can be emulated by
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* broadcast interrupts too. [in case the hw doesn't support APIC timers]
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*
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* [ if a single-CPU system runs an SMP kernel then we call the local
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* interrupt as well. Thus we cannot inline the local irq ... ]
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*/
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void smp_apic_timer_interrupt(struct pt_regs *regs)
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{
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struct pt_regs *old_regs = set_irq_regs(regs);
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|
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/*
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* NOTE! We'd better ACK the irq immediately,
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* because timer handling can be slow.
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*/
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ack_APIC_irq();
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/*
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* update_process_times() expects us to have done irq_enter().
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* Besides, if we don't timer interrupts ignore the global
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* interrupt lock, which is the WrongThing (tm) to do.
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*/
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exit_idle();
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irq_enter();
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local_apic_timer_interrupt();
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irq_exit();
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set_irq_regs(old_regs);
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}
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int setup_profiling_timer(unsigned int multiplier)
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{
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return -EINVAL;
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}
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/*
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* Local APIC start and shutdown
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*/
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/**
|
|
* clear_local_APIC - shutdown the local APIC
|
|
*
|
|
* This is called, when a CPU is disabled and before rebooting, so the state of
|
|
* the local APIC has no dangling leftovers. Also used to cleanout any BIOS
|
|
* leftovers during boot.
|
|
*/
|
|
void clear_local_APIC(void)
|
|
{
|
|
int maxlvt = lapic_get_maxlvt();
|
|
u32 v;
|
|
|
|
/* APIC hasn't been mapped yet */
|
|
if (!apic_phys)
|
|
return;
|
|
|
|
maxlvt = lapic_get_maxlvt();
|
|
/*
|
|
* Masking an LVT entry can trigger a local APIC error
|
|
* if the vector is zero. Mask LVTERR first to prevent this.
|
|
*/
|
|
if (maxlvt >= 3) {
|
|
v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
|
|
apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
|
|
}
|
|
/*
|
|
* Careful: we have to set masks only first to deassert
|
|
* any level-triggered sources.
|
|
*/
|
|
v = apic_read(APIC_LVTT);
|
|
apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
|
|
v = apic_read(APIC_LVT0);
|
|
apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
|
|
v = apic_read(APIC_LVT1);
|
|
apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
|
|
if (maxlvt >= 4) {
|
|
v = apic_read(APIC_LVTPC);
|
|
apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
|
|
}
|
|
|
|
/*
|
|
* Clean APIC state for other OSs:
|
|
*/
|
|
apic_write(APIC_LVTT, APIC_LVT_MASKED);
|
|
apic_write(APIC_LVT0, APIC_LVT_MASKED);
|
|
apic_write(APIC_LVT1, APIC_LVT_MASKED);
|
|
if (maxlvt >= 3)
|
|
apic_write(APIC_LVTERR, APIC_LVT_MASKED);
|
|
if (maxlvt >= 4)
|
|
apic_write(APIC_LVTPC, APIC_LVT_MASKED);
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
}
|
|
|
|
/**
|
|
* disable_local_APIC - clear and disable the local APIC
|
|
*/
|
|
void disable_local_APIC(void)
|
|
{
|
|
unsigned int value;
|
|
|
|
clear_local_APIC();
|
|
|
|
/*
|
|
* Disable APIC (implies clearing of registers
|
|
* for 82489DX!).
|
|
*/
|
|
value = apic_read(APIC_SPIV);
|
|
value &= ~APIC_SPIV_APIC_ENABLED;
|
|
apic_write(APIC_SPIV, value);
|
|
}
|
|
|
|
void lapic_shutdown(void)
|
|
{
|
|
unsigned long flags;
|
|
|
|
if (!cpu_has_apic)
|
|
return;
|
|
|
|
local_irq_save(flags);
|
|
|
|
disable_local_APIC();
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
/*
|
|
* This is to verify that we're looking at a real local APIC.
|
|
* Check these against your board if the CPUs aren't getting
|
|
* started for no apparent reason.
|
|
*/
|
|
int __init verify_local_APIC(void)
|
|
{
|
|
unsigned int reg0, reg1;
|
|
|
|
/*
|
|
* The version register is read-only in a real APIC.
|
|
*/
|
|
reg0 = apic_read(APIC_LVR);
|
|
apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
|
|
apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
|
|
reg1 = apic_read(APIC_LVR);
|
|
apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
|
|
|
|
/*
|
|
* The two version reads above should print the same
|
|
* numbers. If the second one is different, then we
|
|
* poke at a non-APIC.
|
|
*/
|
|
if (reg1 != reg0)
|
|
return 0;
|
|
|
|
/*
|
|
* Check if the version looks reasonably.
|
|
*/
|
|
reg1 = GET_APIC_VERSION(reg0);
|
|
if (reg1 == 0x00 || reg1 == 0xff)
|
|
return 0;
|
|
reg1 = lapic_get_maxlvt();
|
|
if (reg1 < 0x02 || reg1 == 0xff)
|
|
return 0;
|
|
|
|
/*
|
|
* The ID register is read/write in a real APIC.
|
|
*/
|
|
reg0 = apic_read(APIC_ID);
|
|
apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
|
|
apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
|
|
reg1 = apic_read(APIC_ID);
|
|
apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
|
|
apic_write(APIC_ID, reg0);
|
|
if (reg1 != (reg0 ^ APIC_ID_MASK))
|
|
return 0;
|
|
|
|
/*
|
|
* The next two are just to see if we have sane values.
|
|
* They're only really relevant if we're in Virtual Wire
|
|
* compatibility mode, but most boxes are anymore.
|
|
*/
|
|
reg0 = apic_read(APIC_LVT0);
|
|
apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
|
|
reg1 = apic_read(APIC_LVT1);
|
|
apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
|
|
|
|
return 1;
|
|
}
|
|
|
|
/**
|
|
* sync_Arb_IDs - synchronize APIC bus arbitration IDs
|
|
*/
|
|
void __init sync_Arb_IDs(void)
|
|
{
|
|
/* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
|
|
if (modern_apic())
|
|
return;
|
|
|
|
/*
|
|
* Wait for idle.
|
|
*/
|
|
apic_wait_icr_idle();
|
|
|
|
apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
|
|
apic_write(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
|
|
| APIC_DM_INIT);
|
|
}
|
|
|
|
/*
|
|
* An initial setup of the virtual wire mode.
|
|
*/
|
|
void __init init_bsp_APIC(void)
|
|
{
|
|
unsigned int value;
|
|
|
|
/*
|
|
* Don't do the setup now if we have a SMP BIOS as the
|
|
* through-I/O-APIC virtual wire mode might be active.
|
|
*/
|
|
if (smp_found_config || !cpu_has_apic)
|
|
return;
|
|
|
|
value = apic_read(APIC_LVR);
|
|
|
|
/*
|
|
* Do not trust the local APIC being empty at bootup.
|
|
*/
|
|
clear_local_APIC();
|
|
|
|
/*
|
|
* Enable APIC.
|
|
*/
|
|
value = apic_read(APIC_SPIV);
|
|
value &= ~APIC_VECTOR_MASK;
|
|
value |= APIC_SPIV_APIC_ENABLED;
|
|
value |= APIC_SPIV_FOCUS_DISABLED;
|
|
value |= SPURIOUS_APIC_VECTOR;
|
|
apic_write(APIC_SPIV, value);
|
|
|
|
/*
|
|
* Set up the virtual wire mode.
|
|
*/
|
|
apic_write(APIC_LVT0, APIC_DM_EXTINT);
|
|
value = APIC_DM_NMI;
|
|
apic_write(APIC_LVT1, value);
|
|
}
|
|
|
|
/**
|
|
* setup_local_APIC - setup the local APIC
|
|
*/
|
|
void __cpuinit setup_local_APIC(void)
|
|
{
|
|
unsigned int value;
|
|
int i, j;
|
|
|
|
value = apic_read(APIC_LVR);
|
|
|
|
BUILD_BUG_ON((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f);
|
|
|
|
/*
|
|
* Double-check whether this APIC is really registered.
|
|
* This is meaningless in clustered apic mode, so we skip it.
|
|
*/
|
|
if (!apic_id_registered())
|
|
BUG();
|
|
|
|
/*
|
|
* Intel recommends to set DFR, LDR and TPR before enabling
|
|
* an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
|
|
* document number 292116). So here it goes...
|
|
*/
|
|
init_apic_ldr();
|
|
|
|
/*
|
|
* Set Task Priority to 'accept all'. We never change this
|
|
* later on.
|
|
*/
|
|
value = apic_read(APIC_TASKPRI);
|
|
value &= ~APIC_TPRI_MASK;
|
|
apic_write(APIC_TASKPRI, value);
|
|
|
|
/*
|
|
* After a crash, we no longer service the interrupts and a pending
|
|
* interrupt from previous kernel might still have ISR bit set.
|
|
*
|
|
* Most probably by now CPU has serviced that pending interrupt and
|
|
* it might not have done the ack_APIC_irq() because it thought,
|
|
* interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
|
|
* does not clear the ISR bit and cpu thinks it has already serivced
|
|
* the interrupt. Hence a vector might get locked. It was noticed
|
|
* for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
|
|
*/
|
|
for (i = APIC_ISR_NR - 1; i >= 0; i--) {
|
|
value = apic_read(APIC_ISR + i*0x10);
|
|
for (j = 31; j >= 0; j--) {
|
|
if (value & (1<<j))
|
|
ack_APIC_irq();
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Now that we are all set up, enable the APIC
|
|
*/
|
|
value = apic_read(APIC_SPIV);
|
|
value &= ~APIC_VECTOR_MASK;
|
|
/*
|
|
* Enable APIC
|
|
*/
|
|
value |= APIC_SPIV_APIC_ENABLED;
|
|
|
|
/* We always use processor focus */
|
|
|
|
/*
|
|
* Set spurious IRQ vector
|
|
*/
|
|
value |= SPURIOUS_APIC_VECTOR;
|
|
apic_write(APIC_SPIV, value);
|
|
|
|
/*
|
|
* Set up LVT0, LVT1:
|
|
*
|
|
* set up through-local-APIC on the BP's LINT0. This is not
|
|
* strictly necessary in pure symmetric-IO mode, but sometimes
|
|
* we delegate interrupts to the 8259A.
|
|
*/
|
|
/*
|
|
* TODO: set up through-local-APIC from through-I/O-APIC? --macro
|
|
*/
|
|
value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
|
|
if (!smp_processor_id() && !value) {
|
|
value = APIC_DM_EXTINT;
|
|
apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
|
|
smp_processor_id());
|
|
} else {
|
|
value = APIC_DM_EXTINT | APIC_LVT_MASKED;
|
|
apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
|
|
smp_processor_id());
|
|
}
|
|
apic_write(APIC_LVT0, value);
|
|
|
|
/*
|
|
* only the BP should see the LINT1 NMI signal, obviously.
|
|
*/
|
|
if (!smp_processor_id())
|
|
value = APIC_DM_NMI;
|
|
else
|
|
value = APIC_DM_NMI | APIC_LVT_MASKED;
|
|
apic_write(APIC_LVT1, value);
|
|
}
|
|
|
|
void __cpuinit lapic_setup_esr(void)
|
|
{
|
|
unsigned maxlvt = lapic_get_maxlvt();
|
|
|
|
apic_write(APIC_LVTERR, ERROR_APIC_VECTOR);
|
|
/*
|
|
* spec says clear errors after enabling vector.
|
|
*/
|
|
if (maxlvt > 3)
|
|
apic_write(APIC_ESR, 0);
|
|
}
|
|
|
|
void __cpuinit end_local_APIC_setup(void)
|
|
{
|
|
lapic_setup_esr();
|
|
nmi_watchdog_default();
|
|
setup_apic_nmi_watchdog(NULL);
|
|
apic_pm_activate();
|
|
}
|
|
|
|
/*
|
|
* Detect and enable local APICs on non-SMP boards.
|
|
* Original code written by Keir Fraser.
|
|
* On AMD64 we trust the BIOS - if it says no APIC it is likely
|
|
* not correctly set up (usually the APIC timer won't work etc.)
|
|
*/
|
|
static int __init detect_init_APIC(void)
|
|
{
|
|
if (!cpu_has_apic) {
|
|
printk(KERN_INFO "No local APIC present\n");
|
|
return -1;
|
|
}
|
|
|
|
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
|
|
boot_cpu_physical_apicid = 0;
|
|
return 0;
|
|
}
|
|
|
|
void __init early_init_lapic_mapping(void)
|
|
{
|
|
unsigned long apic_phys;
|
|
|
|
/*
|
|
* If no local APIC can be found then go out
|
|
* : it means there is no mpatable and MADT
|
|
*/
|
|
if (!smp_found_config)
|
|
return;
|
|
|
|
apic_phys = mp_lapic_addr;
|
|
|
|
set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
|
|
apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
|
|
APIC_BASE, apic_phys);
|
|
|
|
/*
|
|
* Fetch the APIC ID of the BSP in case we have a
|
|
* default configuration (or the MP table is broken).
|
|
*/
|
|
boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
|
|
}
|
|
|
|
/**
|
|
* init_apic_mappings - initialize APIC mappings
|
|
*/
|
|
void __init init_apic_mappings(void)
|
|
{
|
|
/*
|
|
* If no local APIC can be found then set up a fake all
|
|
* zeroes page to simulate the local APIC and another
|
|
* one for the IO-APIC.
|
|
*/
|
|
if (!smp_found_config && detect_init_APIC()) {
|
|
apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
|
|
apic_phys = __pa(apic_phys);
|
|
} else
|
|
apic_phys = mp_lapic_addr;
|
|
|
|
set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
|
|
apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
|
|
APIC_BASE, apic_phys);
|
|
|
|
/*
|
|
* Fetch the APIC ID of the BSP in case we have a
|
|
* default configuration (or the MP table is broken).
|
|
*/
|
|
boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID));
|
|
}
|
|
|
|
/*
|
|
* This initializes the IO-APIC and APIC hardware if this is
|
|
* a UP kernel.
|
|
*/
|
|
int __init APIC_init_uniprocessor(void)
|
|
{
|
|
if (disable_apic) {
|
|
printk(KERN_INFO "Apic disabled\n");
|
|
return -1;
|
|
}
|
|
if (!cpu_has_apic) {
|
|
disable_apic = 1;
|
|
printk(KERN_INFO "Apic disabled by BIOS\n");
|
|
return -1;
|
|
}
|
|
|
|
verify_local_APIC();
|
|
|
|
phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
|
|
apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
|
|
|
|
setup_local_APIC();
|
|
|
|
/*
|
|
* Now enable IO-APICs, actually call clear_IO_APIC
|
|
* We need clear_IO_APIC before enabling vector on BP
|
|
*/
|
|
if (!skip_ioapic_setup && nr_ioapics)
|
|
enable_IO_APIC();
|
|
|
|
end_local_APIC_setup();
|
|
|
|
if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
|
|
setup_IO_APIC();
|
|
else
|
|
nr_ioapics = 0;
|
|
setup_boot_APIC_clock();
|
|
check_nmi_watchdog();
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Local APIC interrupts
|
|
*/
|
|
|
|
/*
|
|
* This interrupt should _never_ happen with our APIC/SMP architecture
|
|
*/
|
|
asmlinkage void smp_spurious_interrupt(void)
|
|
{
|
|
unsigned int v;
|
|
exit_idle();
|
|
irq_enter();
|
|
/*
|
|
* Check if this really is a spurious interrupt and ACK it
|
|
* if it is a vectored one. Just in case...
|
|
* Spurious interrupts should not be ACKed.
|
|
*/
|
|
v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
|
|
if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
|
|
ack_APIC_irq();
|
|
|
|
add_pda(irq_spurious_count, 1);
|
|
irq_exit();
|
|
}
|
|
|
|
/*
|
|
* This interrupt should never happen with our APIC/SMP architecture
|
|
*/
|
|
asmlinkage void smp_error_interrupt(void)
|
|
{
|
|
unsigned int v, v1;
|
|
|
|
exit_idle();
|
|
irq_enter();
|
|
/* First tickle the hardware, only then report what went on. -- REW */
|
|
v = apic_read(APIC_ESR);
|
|
apic_write(APIC_ESR, 0);
|
|
v1 = apic_read(APIC_ESR);
|
|
ack_APIC_irq();
|
|
atomic_inc(&irq_err_count);
|
|
|
|
/* Here is what the APIC error bits mean:
|
|
0: Send CS error
|
|
1: Receive CS error
|
|
2: Send accept error
|
|
3: Receive accept error
|
|
4: Reserved
|
|
5: Send illegal vector
|
|
6: Received illegal vector
|
|
7: Illegal register address
|
|
*/
|
|
printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
|
|
smp_processor_id(), v , v1);
|
|
irq_exit();
|
|
}
|
|
|
|
void disconnect_bsp_APIC(int virt_wire_setup)
|
|
{
|
|
/* Go back to Virtual Wire compatibility mode */
|
|
unsigned long value;
|
|
|
|
/* For the spurious interrupt use vector F, and enable it */
|
|
value = apic_read(APIC_SPIV);
|
|
value &= ~APIC_VECTOR_MASK;
|
|
value |= APIC_SPIV_APIC_ENABLED;
|
|
value |= 0xf;
|
|
apic_write(APIC_SPIV, value);
|
|
|
|
if (!virt_wire_setup) {
|
|
/*
|
|
* For LVT0 make it edge triggered, active high,
|
|
* external and enabled
|
|
*/
|
|
value = apic_read(APIC_LVT0);
|
|
value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
|
|
APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
|
|
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
|
|
value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
|
|
value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
|
|
apic_write(APIC_LVT0, value);
|
|
} else {
|
|
/* Disable LVT0 */
|
|
apic_write(APIC_LVT0, APIC_LVT_MASKED);
|
|
}
|
|
|
|
/* For LVT1 make it edge triggered, active high, nmi and enabled */
|
|
value = apic_read(APIC_LVT1);
|
|
value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
|
|
APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
|
|
APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
|
|
value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
|
|
value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
|
|
apic_write(APIC_LVT1, value);
|
|
}
|
|
|
|
/*
|
|
* Power management
|
|
*/
|
|
#ifdef CONFIG_PM
|
|
|
|
static struct {
|
|
/* 'active' is true if the local APIC was enabled by us and
|
|
not the BIOS; this signifies that we are also responsible
|
|
for disabling it before entering apm/acpi suspend */
|
|
int active;
|
|
/* r/w apic fields */
|
|
unsigned int apic_id;
|
|
unsigned int apic_taskpri;
|
|
unsigned int apic_ldr;
|
|
unsigned int apic_dfr;
|
|
unsigned int apic_spiv;
|
|
unsigned int apic_lvtt;
|
|
unsigned int apic_lvtpc;
|
|
unsigned int apic_lvt0;
|
|
unsigned int apic_lvt1;
|
|
unsigned int apic_lvterr;
|
|
unsigned int apic_tmict;
|
|
unsigned int apic_tdcr;
|
|
unsigned int apic_thmr;
|
|
} apic_pm_state;
|
|
|
|
static int lapic_suspend(struct sys_device *dev, pm_message_t state)
|
|
{
|
|
unsigned long flags;
|
|
int maxlvt;
|
|
|
|
if (!apic_pm_state.active)
|
|
return 0;
|
|
|
|
maxlvt = lapic_get_maxlvt();
|
|
|
|
apic_pm_state.apic_id = apic_read(APIC_ID);
|
|
apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
|
|
apic_pm_state.apic_ldr = apic_read(APIC_LDR);
|
|
apic_pm_state.apic_dfr = apic_read(APIC_DFR);
|
|
apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
|
|
apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
|
|
if (maxlvt >= 4)
|
|
apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
|
|
apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
|
|
apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
|
|
apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
|
|
apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
|
|
apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
|
|
#ifdef CONFIG_X86_MCE_INTEL
|
|
if (maxlvt >= 5)
|
|
apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
|
|
#endif
|
|
local_irq_save(flags);
|
|
disable_local_APIC();
|
|
local_irq_restore(flags);
|
|
return 0;
|
|
}
|
|
|
|
static int lapic_resume(struct sys_device *dev)
|
|
{
|
|
unsigned int l, h;
|
|
unsigned long flags;
|
|
int maxlvt;
|
|
|
|
if (!apic_pm_state.active)
|
|
return 0;
|
|
|
|
maxlvt = lapic_get_maxlvt();
|
|
|
|
local_irq_save(flags);
|
|
rdmsr(MSR_IA32_APICBASE, l, h);
|
|
l &= ~MSR_IA32_APICBASE_BASE;
|
|
l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
|
|
wrmsr(MSR_IA32_APICBASE, l, h);
|
|
apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
|
|
apic_write(APIC_ID, apic_pm_state.apic_id);
|
|
apic_write(APIC_DFR, apic_pm_state.apic_dfr);
|
|
apic_write(APIC_LDR, apic_pm_state.apic_ldr);
|
|
apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
|
|
apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
|
|
apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
|
|
apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
|
|
#ifdef CONFIG_X86_MCE_INTEL
|
|
if (maxlvt >= 5)
|
|
apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
|
|
#endif
|
|
if (maxlvt >= 4)
|
|
apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
|
|
apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
|
|
apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
|
|
apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
|
|
apic_write(APIC_ESR, 0);
|
|
apic_read(APIC_ESR);
|
|
local_irq_restore(flags);
|
|
return 0;
|
|
}
|
|
|
|
static struct sysdev_class lapic_sysclass = {
|
|
.name = "lapic",
|
|
.resume = lapic_resume,
|
|
.suspend = lapic_suspend,
|
|
};
|
|
|
|
static struct sys_device device_lapic = {
|
|
.id = 0,
|
|
.cls = &lapic_sysclass,
|
|
};
|
|
|
|
static void __cpuinit apic_pm_activate(void)
|
|
{
|
|
apic_pm_state.active = 1;
|
|
}
|
|
|
|
static int __init init_lapic_sysfs(void)
|
|
{
|
|
int error;
|
|
|
|
if (!cpu_has_apic)
|
|
return 0;
|
|
/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
|
|
|
|
error = sysdev_class_register(&lapic_sysclass);
|
|
if (!error)
|
|
error = sysdev_register(&device_lapic);
|
|
return error;
|
|
}
|
|
device_initcall(init_lapic_sysfs);
|
|
|
|
#else /* CONFIG_PM */
|
|
|
|
static void apic_pm_activate(void) { }
|
|
|
|
#endif /* CONFIG_PM */
|
|
|
|
/*
|
|
* apic_is_clustered_box() -- Check if we can expect good TSC
|
|
*
|
|
* Thus far, the major user of this is IBM's Summit2 series:
|
|
*
|
|
* Clustered boxes may have unsynced TSC problems if they are
|
|
* multi-chassis. Use available data to take a good guess.
|
|
* If in doubt, go HPET.
|
|
*/
|
|
__cpuinit int apic_is_clustered_box(void)
|
|
{
|
|
int i, clusters, zeros;
|
|
unsigned id;
|
|
u16 *bios_cpu_apicid;
|
|
DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
|
|
|
|
/*
|
|
* there is not this kind of box with AMD CPU yet.
|
|
* Some AMD box with quadcore cpu and 8 sockets apicid
|
|
* will be [4, 0x23] or [8, 0x27] could be thought to
|
|
* vsmp box still need checking...
|
|
*/
|
|
if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
|
|
return 0;
|
|
|
|
bios_cpu_apicid = x86_bios_cpu_apicid_early_ptr;
|
|
bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
|
|
|
|
for (i = 0; i < NR_CPUS; i++) {
|
|
/* are we being called early in kernel startup? */
|
|
if (bios_cpu_apicid) {
|
|
id = bios_cpu_apicid[i];
|
|
}
|
|
else if (i < nr_cpu_ids) {
|
|
if (cpu_present(i))
|
|
id = per_cpu(x86_bios_cpu_apicid, i);
|
|
else
|
|
continue;
|
|
}
|
|
else
|
|
break;
|
|
|
|
if (id != BAD_APICID)
|
|
__set_bit(APIC_CLUSTERID(id), clustermap);
|
|
}
|
|
|
|
/* Problem: Partially populated chassis may not have CPUs in some of
|
|
* the APIC clusters they have been allocated. Only present CPUs have
|
|
* x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
|
|
* Since clusters are allocated sequentially, count zeros only if
|
|
* they are bounded by ones.
|
|
*/
|
|
clusters = 0;
|
|
zeros = 0;
|
|
for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
|
|
if (test_bit(i, clustermap)) {
|
|
clusters += 1 + zeros;
|
|
zeros = 0;
|
|
} else
|
|
++zeros;
|
|
}
|
|
|
|
/* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
|
|
* not guaranteed to be synced between boards
|
|
*/
|
|
if (is_vsmp_box() && clusters > 1)
|
|
return 1;
|
|
|
|
/*
|
|
* If clusters > 2, then should be multi-chassis.
|
|
* May have to revisit this when multi-core + hyperthreaded CPUs come
|
|
* out, but AFAIK this will work even for them.
|
|
*/
|
|
return (clusters > 2);
|
|
}
|
|
|
|
/*
|
|
* APIC command line parameters
|
|
*/
|
|
static int __init apic_set_verbosity(char *str)
|
|
{
|
|
if (str == NULL) {
|
|
skip_ioapic_setup = 0;
|
|
ioapic_force = 1;
|
|
return 0;
|
|
}
|
|
if (strcmp("debug", str) == 0)
|
|
apic_verbosity = APIC_DEBUG;
|
|
else if (strcmp("verbose", str) == 0)
|
|
apic_verbosity = APIC_VERBOSE;
|
|
else {
|
|
printk(KERN_WARNING "APIC Verbosity level %s not recognised"
|
|
" use apic=verbose or apic=debug\n", str);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
early_param("apic", apic_set_verbosity);
|
|
|
|
static __init int setup_disableapic(char *str)
|
|
{
|
|
disable_apic = 1;
|
|
clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
|
|
return 0;
|
|
}
|
|
early_param("disableapic", setup_disableapic);
|
|
|
|
/* same as disableapic, for compatibility */
|
|
static __init int setup_nolapic(char *str)
|
|
{
|
|
return setup_disableapic(str);
|
|
}
|
|
early_param("nolapic", setup_nolapic);
|
|
|
|
static int __init parse_lapic_timer_c2_ok(char *arg)
|
|
{
|
|
local_apic_timer_c2_ok = 1;
|
|
return 0;
|
|
}
|
|
early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
|
|
|
|
static __init int setup_noapictimer(char *str)
|
|
{
|
|
if (str[0] != ' ' && str[0] != 0)
|
|
return 0;
|
|
disable_apic_timer = 1;
|
|
return 1;
|
|
}
|
|
__setup("noapictimer", setup_noapictimer);
|
|
|
|
static __init int setup_apicpmtimer(char *s)
|
|
{
|
|
apic_calibrate_pmtmr = 1;
|
|
notsc_setup(NULL);
|
|
return 0;
|
|
}
|
|
__setup("apicpmtimer", setup_apicpmtimer);
|
|
|
|
static int __init lapic_insert_resource(void)
|
|
{
|
|
if (!apic_phys)
|
|
return -1;
|
|
|
|
/* Put local APIC into the resource map. */
|
|
lapic_resource.start = apic_phys;
|
|
lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
|
|
insert_resource(&iomem_resource, &lapic_resource);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* need call insert after e820_reserve_resources()
|
|
* that is using request_resource
|
|
*/
|
|
late_initcall(lapic_insert_resource);
|