a36ed2995c
Replace the chip lock by a the controller lock. For simple drivers a dummy controller structure is created by the scan code. This simplifies the locking algorithm in nand_get/release_chip(). Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
514 lines
19 KiB
C
514 lines
19 KiB
C
/*
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* linux/include/linux/mtd/nand.h
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*
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* Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
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* Steven J. Hill <sjhill@realitydiluted.com>
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* Thomas Gleixner <tglx@linutronix.de>
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*
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* $Id: nand.h,v 1.74 2005/09/15 13:58:50 vwool Exp $
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Info:
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* Contains standard defines and IDs for NAND flash devices
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*
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* Changelog:
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* 01-31-2000 DMW Created
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* 09-18-2000 SJH Moved structure out of the Disk-On-Chip drivers
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* so it can be used by other NAND flash device
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* drivers. I also changed the copyright since none
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* of the original contents of this file are specific
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* to DoC devices. David can whack me with a baseball
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* bat later if I did something naughty.
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* 10-11-2000 SJH Added private NAND flash structure for driver
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* 10-24-2000 SJH Added prototype for 'nand_scan' function
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* 10-29-2001 TG changed nand_chip structure to support
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* hardwarespecific function for accessing control lines
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* 02-21-2002 TG added support for different read/write adress and
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* ready/busy line access function
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* 02-26-2002 TG added chip_delay to nand_chip structure to optimize
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* command delay times for different chips
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* 04-28-2002 TG OOB config defines moved from nand.c to avoid duplicate
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* defines in jffs2/wbuf.c
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* 08-07-2002 TG forced bad block location to byte 5 of OOB, even if
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* CONFIG_MTD_NAND_ECC_JFFS2 is not set
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* 08-10-2002 TG extensions to nand_chip structure to support HW-ECC
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*
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* 08-29-2002 tglx nand_chip structure: data_poi for selecting
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* internal / fs-driver buffer
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* support for 6byte/512byte hardware ECC
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* read_ecc, write_ecc extended for different oob-layout
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* oob layout selections: NAND_NONE_OOB, NAND_JFFS2_OOB,
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* NAND_YAFFS_OOB
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* 11-25-2002 tglx Added Manufacturer code FUJITSU, NATIONAL
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* Split manufacturer and device ID structures
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*
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* 02-08-2004 tglx added option field to nand structure for chip anomalities
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* 05-25-2004 tglx added bad block table support, ST-MICRO manufacturer id
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* update of nand_chip structure description
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* 01-17-2005 dmarlin added extended commands for AG-AND device and added option
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* for BBT_AUTO_REFRESH.
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* 01-20-2005 dmarlin added optional pointer to hardware specific callback for
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* extra error status checks.
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*/
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#ifndef __LINUX_MTD_NAND_H
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#define __LINUX_MTD_NAND_H
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#include <linux/config.h>
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#include <linux/wait.h>
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#include <linux/spinlock.h>
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#include <linux/mtd/mtd.h>
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struct mtd_info;
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/* Scan and identify a NAND device */
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extern int nand_scan (struct mtd_info *mtd, int max_chips);
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/* Free resources held by the NAND device */
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extern void nand_release (struct mtd_info *mtd);
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/* Read raw data from the device without ECC */
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extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_t len, size_t ooblen);
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/* The maximum number of NAND chips in an array */
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#define NAND_MAX_CHIPS 8
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/* This constant declares the max. oobsize / page, which
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* is supported now. If you add a chip with bigger oobsize/page
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* adjust this accordingly.
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*/
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#define NAND_MAX_OOBSIZE 64
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/*
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* Constants for hardware specific CLE/ALE/NCE function
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*/
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/* Select the chip by setting nCE to low */
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#define NAND_CTL_SETNCE 1
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/* Deselect the chip by setting nCE to high */
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#define NAND_CTL_CLRNCE 2
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/* Select the command latch by setting CLE to high */
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#define NAND_CTL_SETCLE 3
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/* Deselect the command latch by setting CLE to low */
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#define NAND_CTL_CLRCLE 4
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/* Select the address latch by setting ALE to high */
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#define NAND_CTL_SETALE 5
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/* Deselect the address latch by setting ALE to low */
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#define NAND_CTL_CLRALE 6
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/* Set write protection by setting WP to high. Not used! */
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#define NAND_CTL_SETWP 7
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/* Clear write protection by setting WP to low. Not used! */
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#define NAND_CTL_CLRWP 8
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/*
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* Standard NAND flash commands
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*/
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#define NAND_CMD_READ0 0
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#define NAND_CMD_READ1 1
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#define NAND_CMD_PAGEPROG 0x10
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#define NAND_CMD_READOOB 0x50
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#define NAND_CMD_ERASE1 0x60
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_SEQIN 0x80
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#define NAND_CMD_READID 0x90
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#define NAND_CMD_ERASE2 0xd0
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#define NAND_CMD_RESET 0xff
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/* Extended commands for large page devices */
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#define NAND_CMD_READSTART 0x30
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#define NAND_CMD_CACHEDPROG 0x15
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/* Extended commands for AG-AND device */
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/*
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* Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
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* there is no way to distinguish that from NAND_CMD_READ0
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* until the remaining sequence of commands has been completed
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* so add a high order bit and mask it off in the command.
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*/
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#define NAND_CMD_DEPLETE1 0x100
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#define NAND_CMD_DEPLETE2 0x38
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#define NAND_CMD_STATUS_MULTI 0x71
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#define NAND_CMD_STATUS_ERROR 0x72
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/* multi-bank error status (banks 0-3) */
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#define NAND_CMD_STATUS_ERROR0 0x73
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#define NAND_CMD_STATUS_ERROR1 0x74
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#define NAND_CMD_STATUS_ERROR2 0x75
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#define NAND_CMD_STATUS_ERROR3 0x76
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#define NAND_CMD_STATUS_RESET 0x7f
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#define NAND_CMD_STATUS_CLEAR 0xff
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/* Status bits */
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#define NAND_STATUS_FAIL 0x01
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#define NAND_STATUS_FAIL_N1 0x02
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#define NAND_STATUS_TRUE_READY 0x20
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#define NAND_STATUS_READY 0x40
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#define NAND_STATUS_WP 0x80
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/*
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* Constants for ECC_MODES
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*/
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/* No ECC. Usage is not recommended ! */
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#define NAND_ECC_NONE 0
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/* Software ECC 3 byte ECC per 256 Byte data */
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#define NAND_ECC_SOFT 1
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/* Hardware ECC 3 byte ECC per 256 Byte data */
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#define NAND_ECC_HW3_256 2
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/* Hardware ECC 3 byte ECC per 512 Byte data */
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#define NAND_ECC_HW3_512 3
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/* Hardware ECC 3 byte ECC per 512 Byte data */
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#define NAND_ECC_HW6_512 4
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/* Hardware ECC 8 byte ECC per 512 Byte data */
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#define NAND_ECC_HW8_512 6
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/* Hardware ECC 12 byte ECC per 2048 Byte data */
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#define NAND_ECC_HW12_2048 7
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/*
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* Constants for Hardware ECC
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*/
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/* Reset Hardware ECC for read */
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#define NAND_ECC_READ 0
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/* Reset Hardware ECC for write */
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#define NAND_ECC_WRITE 1
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/* Enable Hardware ECC before syndrom is read back from flash */
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#define NAND_ECC_READSYN 2
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/* Bit mask for flags passed to do_nand_read_ecc */
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#define NAND_GET_DEVICE 0x80
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/* Option constants for bizarre disfunctionality and real
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* features
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*/
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/* Chip can not auto increment pages */
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#define NAND_NO_AUTOINCR 0x00000001
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/* Buswitdh is 16 bit */
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#define NAND_BUSWIDTH_16 0x00000002
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/* Device supports partial programming without padding */
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#define NAND_NO_PADDING 0x00000004
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/* Chip has cache program function */
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#define NAND_CACHEPRG 0x00000008
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/* Chip has copy back function */
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#define NAND_COPYBACK 0x00000010
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/* AND Chip which has 4 banks and a confusing page / block
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* assignment. See Renesas datasheet for further information */
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#define NAND_IS_AND 0x00000020
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/* Chip has a array of 4 pages which can be read without
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* additional ready /busy waits */
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#define NAND_4PAGE_ARRAY 0x00000040
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/* Chip requires that BBT is periodically rewritten to prevent
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* bits from adjacent blocks from 'leaking' in altering data.
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* This happens with the Renesas AG-AND chips, possibly others. */
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#define BBT_AUTO_REFRESH 0x00000080
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/* Options valid for Samsung large page devices */
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#define NAND_SAMSUNG_LP_OPTIONS \
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(NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
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/* Macros to identify the above */
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#define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
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#define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
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#define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
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#define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
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/* Mask to zero out the chip options, which come from the id table */
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#define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
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/* Non chip related options */
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/* Use a flash based bad block table. This option is passed to the
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* default bad block table function. */
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#define NAND_USE_FLASH_BBT 0x00010000
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/* The hw ecc generator provides a syndrome instead a ecc value on read
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* This can only work if we have the ecc bytes directly behind the
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* data bytes. Applies for DOC and AG-AND Renesas HW Reed Solomon generators */
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#define NAND_HWECC_SYNDROME 0x00020000
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/* This option skips the bbt scan during initialization. */
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#define NAND_SKIP_BBTSCAN 0x00040000
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/* Options set by nand scan */
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/* Nand scan has allocated controller struct */
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#define NAND_CONTROLLER_ALLOC 0x20000000
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/* Nand scan has allocated oob_buf */
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#define NAND_OOBBUF_ALLOC 0x40000000
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/* Nand scan has allocated data_buf */
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#define NAND_DATABUF_ALLOC 0x80000000
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/*
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* nand_state_t - chip states
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* Enumeration for NAND flash chip state
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*/
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typedef enum {
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FL_READY,
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FL_READING,
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FL_WRITING,
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FL_ERASING,
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FL_SYNCING,
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FL_CACHEDPRG,
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FL_PM_SUSPENDED,
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} nand_state_t;
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/* Keep gcc happy */
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struct nand_chip;
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/**
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* struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independend devices
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* @lock: protection lock
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* @active: the mtd device which holds the controller currently
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* @wq: wait queue to sleep on if a NAND operation is in progress
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* used instead of the per chip wait queue when a hw controller is available
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*/
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struct nand_hw_control {
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spinlock_t lock;
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struct nand_chip *active;
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wait_queue_head_t wq;
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};
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/**
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* struct nand_chip - NAND Private Flash Chip Data
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* @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
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* @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
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* @read_byte: [REPLACEABLE] read one byte from the chip
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* @write_byte: [REPLACEABLE] write one byte to the chip
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* @read_word: [REPLACEABLE] read one word from the chip
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* @write_word: [REPLACEABLE] write one word to the chip
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* @write_buf: [REPLACEABLE] write data from the buffer to the chip
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* @read_buf: [REPLACEABLE] read data from the chip into the buffer
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* @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
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* @select_chip: [REPLACEABLE] select chip nr
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* @block_bad: [REPLACEABLE] check, if the block is bad
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* @block_markbad: [REPLACEABLE] mark the block bad
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* @hwcontrol: [BOARDSPECIFIC] hardwarespecific function for accesing control-lines
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* @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
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* If set to NULL no access to ready/busy is available and the ready/busy information
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* is read from the chip status register
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* @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
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* @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
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* @calculate_ecc: [REPLACEABLE] function for ecc calculation or readback from ecc hardware
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* @correct_data: [REPLACEABLE] function for ecc correction, matching to ecc generator (sw/hw)
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* @enable_hwecc: [BOARDSPECIFIC] function to enable (reset) hardware ecc generator. Must only
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* be provided if a hardware ECC is available
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* @erase_cmd: [INTERN] erase command write function, selectable due to AND support
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* @scan_bbt: [REPLACEABLE] function to scan bad block table
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* @eccmode: [BOARDSPECIFIC] mode of ecc, see defines
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* @eccsize: [INTERN] databytes used per ecc-calculation
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* @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
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* @eccsteps: [INTERN] number of ecc calculation steps per page
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* @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
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* @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
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* @state: [INTERN] the current state of the NAND device
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* @page_shift: [INTERN] number of address bits in a page (column address bits)
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* @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
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* @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
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* @chip_shift: [INTERN] number of address bits in one chip
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* @data_buf: [INTERN] internal buffer for one page + oob
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* @oob_buf: [INTERN] oob buffer for one eraseblock
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* @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
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* @data_poi: [INTERN] pointer to a data buffer
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* @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
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* special functionality. See the defines for further explanation
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* @badblockpos: [INTERN] position of the bad block marker in the oob area
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* @numchips: [INTERN] number of physical chips
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* @chipsize: [INTERN] the size of one chip for multichip arrays
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* @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
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* @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
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* @autooob: [REPLACEABLE] the default (auto)placement scheme
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* @bbt: [INTERN] bad block table pointer
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* @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
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* @bbt_md: [REPLACEABLE] bad block table mirror descriptor
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* @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
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* @controller: [REPLACEABLE] a pointer to a hardware controller structure
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* which is shared among multiple independend devices
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* @priv: [OPTIONAL] pointer to private chip date
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* @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
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* (determine if errors are correctable)
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*/
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struct nand_chip {
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void __iomem *IO_ADDR_R;
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void __iomem *IO_ADDR_W;
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u_char (*read_byte)(struct mtd_info *mtd);
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void (*write_byte)(struct mtd_info *mtd, u_char byte);
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u16 (*read_word)(struct mtd_info *mtd);
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void (*write_word)(struct mtd_info *mtd, u16 word);
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void (*write_buf)(struct mtd_info *mtd, const u_char *buf, int len);
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void (*read_buf)(struct mtd_info *mtd, u_char *buf, int len);
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int (*verify_buf)(struct mtd_info *mtd, const u_char *buf, int len);
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void (*select_chip)(struct mtd_info *mtd, int chip);
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int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
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int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
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void (*hwcontrol)(struct mtd_info *mtd, int cmd);
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int (*dev_ready)(struct mtd_info *mtd);
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void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
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int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this, int state);
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int (*calculate_ecc)(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code);
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int (*correct_data)(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc);
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void (*enable_hwecc)(struct mtd_info *mtd, int mode);
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void (*erase_cmd)(struct mtd_info *mtd, int page);
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int (*scan_bbt)(struct mtd_info *mtd);
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int eccmode;
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int eccsize;
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int eccbytes;
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int eccsteps;
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int chip_delay;
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wait_queue_head_t wq;
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nand_state_t state;
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int page_shift;
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int phys_erase_shift;
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int bbt_erase_shift;
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int chip_shift;
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u_char *data_buf;
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u_char *oob_buf;
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int oobdirty;
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u_char *data_poi;
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unsigned int options;
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int badblockpos;
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int numchips;
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unsigned long chipsize;
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int pagemask;
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int pagebuf;
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struct nand_oobinfo *autooob;
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uint8_t *bbt;
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struct nand_bbt_descr *bbt_td;
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struct nand_bbt_descr *bbt_md;
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struct nand_bbt_descr *badblock_pattern;
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struct nand_hw_control *controller;
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void *priv;
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int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
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};
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/*
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* NAND Flash Manufacturer ID Codes
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*/
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#define NAND_MFR_TOSHIBA 0x98
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#define NAND_MFR_SAMSUNG 0xec
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#define NAND_MFR_FUJITSU 0x04
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#define NAND_MFR_NATIONAL 0x8f
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#define NAND_MFR_RENESAS 0x07
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#define NAND_MFR_STMICRO 0x20
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#define NAND_MFR_HYNIX 0xad
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/**
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* struct nand_flash_dev - NAND Flash Device ID Structure
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*
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* @name: Identify the device type
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* @id: device ID code
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* @pagesize: Pagesize in bytes. Either 256 or 512 or 0
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* If the pagesize is 0, then the real pagesize
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* and the eraseize are determined from the
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* extended id bytes in the chip
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* @erasesize: Size of an erase block in the flash device.
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* @chipsize: Total chipsize in Mega Bytes
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* @options: Bitfield to store chip relevant options
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*/
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struct nand_flash_dev {
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char *name;
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int id;
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unsigned long pagesize;
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unsigned long chipsize;
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unsigned long erasesize;
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unsigned long options;
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};
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/**
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* struct nand_manufacturers - NAND Flash Manufacturer ID Structure
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* @name: Manufacturer name
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* @id: manufacturer ID code of device.
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*/
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struct nand_manufacturers {
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int id;
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char * name;
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};
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extern struct nand_flash_dev nand_flash_ids[];
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extern struct nand_manufacturers nand_manuf_ids[];
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|
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/**
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* struct nand_bbt_descr - bad block table descriptor
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|
* @options: options for this descriptor
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|
* @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
|
|
* when bbt is searched, then we store the found bbts pages here.
|
|
* Its an array and supports up to 8 chips now
|
|
* @offs: offset of the pattern in the oob area of the page
|
|
* @veroffs: offset of the bbt version counter in the oob are of the page
|
|
* @version: version read from the bbt page during scan
|
|
* @len: length of the pattern, if 0 no pattern check is performed
|
|
* @maxblocks: maximum number of blocks to search for a bbt. This number of
|
|
* blocks is reserved at the end of the device where the tables are
|
|
* written.
|
|
* @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
|
|
* bad) block in the stored bbt
|
|
* @pattern: pattern to identify bad block table or factory marked good /
|
|
* bad blocks, can be NULL, if len = 0
|
|
*
|
|
* Descriptor for the bad block table marker and the descriptor for the
|
|
* pattern which identifies good and bad blocks. The assumption is made
|
|
* that the pattern and the version count are always located in the oob area
|
|
* of the first block.
|
|
*/
|
|
struct nand_bbt_descr {
|
|
int options;
|
|
int pages[NAND_MAX_CHIPS];
|
|
int offs;
|
|
int veroffs;
|
|
uint8_t version[NAND_MAX_CHIPS];
|
|
int len;
|
|
int maxblocks;
|
|
int reserved_block_code;
|
|
uint8_t *pattern;
|
|
};
|
|
|
|
/* Options for the bad block table descriptors */
|
|
|
|
/* The number of bits used per block in the bbt on the device */
|
|
#define NAND_BBT_NRBITS_MSK 0x0000000F
|
|
#define NAND_BBT_1BIT 0x00000001
|
|
#define NAND_BBT_2BIT 0x00000002
|
|
#define NAND_BBT_4BIT 0x00000004
|
|
#define NAND_BBT_8BIT 0x00000008
|
|
/* The bad block table is in the last good block of the device */
|
|
#define NAND_BBT_LASTBLOCK 0x00000010
|
|
/* The bbt is at the given page, else we must scan for the bbt */
|
|
#define NAND_BBT_ABSPAGE 0x00000020
|
|
/* The bbt is at the given page, else we must scan for the bbt */
|
|
#define NAND_BBT_SEARCH 0x00000040
|
|
/* bbt is stored per chip on multichip devices */
|
|
#define NAND_BBT_PERCHIP 0x00000080
|
|
/* bbt has a version counter at offset veroffs */
|
|
#define NAND_BBT_VERSION 0x00000100
|
|
/* Create a bbt if none axists */
|
|
#define NAND_BBT_CREATE 0x00000200
|
|
/* Search good / bad pattern through all pages of a block */
|
|
#define NAND_BBT_SCANALLPAGES 0x00000400
|
|
/* Scan block empty during good / bad block scan */
|
|
#define NAND_BBT_SCANEMPTY 0x00000800
|
|
/* Write bbt if neccecary */
|
|
#define NAND_BBT_WRITE 0x00001000
|
|
/* Read and write back block contents when writing bbt */
|
|
#define NAND_BBT_SAVECONTENT 0x00002000
|
|
/* Search good / bad pattern on the first and the second page */
|
|
#define NAND_BBT_SCAN2NDPAGE 0x00004000
|
|
|
|
/* The maximum number of blocks to scan for a bbt */
|
|
#define NAND_BBT_SCAN_MAXBLOCKS 4
|
|
|
|
extern int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd);
|
|
extern int nand_update_bbt (struct mtd_info *mtd, loff_t offs);
|
|
extern int nand_default_bbt (struct mtd_info *mtd);
|
|
extern int nand_isbad_bbt (struct mtd_info *mtd, loff_t offs, int allowbbt);
|
|
extern int nand_erase_nand (struct mtd_info *mtd, struct erase_info *instr, int allowbbt);
|
|
extern int nand_do_read_ecc (struct mtd_info *mtd, loff_t from, size_t len,
|
|
size_t * retlen, u_char * buf, u_char * oob_buf,
|
|
struct nand_oobinfo *oobsel, int flags);
|
|
|
|
/*
|
|
* Constants for oob configuration
|
|
*/
|
|
#define NAND_SMALL_BADBLOCK_POS 5
|
|
#define NAND_LARGE_BADBLOCK_POS 0
|
|
|
|
#endif /* __LINUX_MTD_NAND_H */
|