a3d7f85f47
This reduces overhead by accessing cachelines from the wrong node, as well as simplifying locking. [Qing: fix for inactive or expired one-shot timer] Signed-off-by: Yaozu (Eddie) Dong <Eddie.Dong@intel.com> Signed-off-by: Qing He <qing.he@intel.com> Signed-off-by: Avi Kivity <avi@qumranet.com>
164 lines
4.8 KiB
C
164 lines
4.8 KiB
C
/*
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* irq.h: in kernel interrupt controller related definitions
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* Copyright (c) 2007, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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* Authors:
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* Yaozu (Eddie) Dong <Eddie.dong@intel.com>
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*
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*/
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#ifndef __IRQ_H
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#define __IRQ_H
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#include "kvm.h"
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typedef void irq_request_func(void *opaque, int level);
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struct kvm_kpic_state {
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u8 last_irr; /* edge detection */
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u8 irr; /* interrupt request register */
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u8 imr; /* interrupt mask register */
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u8 isr; /* interrupt service register */
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u8 priority_add; /* highest irq priority */
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u8 irq_base;
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u8 read_reg_select;
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u8 poll;
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u8 special_mask;
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u8 init_state;
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u8 auto_eoi;
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u8 rotate_on_auto_eoi;
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u8 special_fully_nested_mode;
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u8 init4; /* true if 4 byte init */
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u8 elcr; /* PIIX edge/trigger selection */
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u8 elcr_mask;
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struct kvm_pic *pics_state;
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};
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struct kvm_pic {
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struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */
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irq_request_func *irq_request;
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void *irq_request_opaque;
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int output; /* intr from master PIC */
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struct kvm_io_device dev;
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};
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struct kvm_pic *kvm_create_pic(struct kvm *kvm);
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void kvm_pic_set_irq(void *opaque, int irq, int level);
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int kvm_pic_read_irq(struct kvm_pic *s);
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int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
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int kvm_cpu_has_interrupt(struct kvm_vcpu *v);
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void kvm_pic_update_irq(struct kvm_pic *s);
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#define IOAPIC_NUM_PINS KVM_IOAPIC_NUM_PINS
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#define IOAPIC_VERSION_ID 0x11 /* IOAPIC version */
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#define IOAPIC_EDGE_TRIG 0
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#define IOAPIC_LEVEL_TRIG 1
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#define IOAPIC_DEFAULT_BASE_ADDRESS 0xfec00000
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#define IOAPIC_MEM_LENGTH 0x100
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/* Direct registers. */
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#define IOAPIC_REG_SELECT 0x00
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#define IOAPIC_REG_WINDOW 0x10
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#define IOAPIC_REG_EOI 0x40 /* IA64 IOSAPIC only */
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/* Indirect registers. */
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#define IOAPIC_REG_APIC_ID 0x00 /* x86 IOAPIC only */
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#define IOAPIC_REG_VERSION 0x01
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#define IOAPIC_REG_ARB_ID 0x02 /* x86 IOAPIC only */
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struct kvm_ioapic {
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u64 base_address;
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u32 ioregsel;
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u32 id;
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u32 irr;
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u32 pad;
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union ioapic_redir_entry {
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u64 bits;
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struct {
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u8 vector;
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u8 delivery_mode:3;
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u8 dest_mode:1;
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u8 delivery_status:1;
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u8 polarity:1;
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u8 remote_irr:1;
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u8 trig_mode:1;
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u8 mask:1;
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u8 reserve:7;
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u8 reserved[4];
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u8 dest_id;
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} fields;
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} redirtbl[IOAPIC_NUM_PINS];
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struct kvm_io_device dev;
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struct kvm *kvm;
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};
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struct kvm_lapic {
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unsigned long base_address;
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struct kvm_io_device dev;
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struct {
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atomic_t pending;
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s64 period; /* unit: ns */
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u32 divide_count;
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ktime_t last_update;
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struct hrtimer dev;
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} timer;
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struct kvm_vcpu *vcpu;
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struct page *regs_page;
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void *regs;
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};
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#ifdef DEBUG
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#define ASSERT(x) \
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do { \
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if (!(x)) { \
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printk(KERN_EMERG "assertion failed %s: %d: %s\n", \
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__FILE__, __LINE__, #x); \
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BUG(); \
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} \
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} while (0)
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#else
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#define ASSERT(x) do { } while (0)
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#endif
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void kvm_vcpu_kick(struct kvm_vcpu *vcpu);
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int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu);
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int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu);
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int kvm_create_lapic(struct kvm_vcpu *vcpu);
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void kvm_free_apic(struct kvm_lapic *apic);
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u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
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void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
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void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
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struct kvm_lapic *kvm_apic_round_robin(struct kvm *kvm, u8 vector,
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unsigned long bitmap);
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u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
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void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
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int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
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void kvm_ioapic_update_eoi(struct kvm *kvm, int vector);
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int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
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int kvm_apic_set_irq(struct kvm_lapic *apic, u8 vec, u8 trig);
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void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu);
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int kvm_ioapic_init(struct kvm *kvm);
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void kvm_ioapic_set_irq(struct kvm_ioapic *ioapic, int irq, int level);
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int kvm_lapic_enabled(struct kvm_vcpu *vcpu);
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int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
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void kvm_apic_timer_intr_post(struct kvm_vcpu *vcpu, int vec);
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void kvm_timer_intr_post(struct kvm_vcpu *vcpu, int vec);
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void kvm_inject_pending_timer_irqs(struct kvm_vcpu *vcpu);
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void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu);
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void kvm_migrate_apic_timer(struct kvm_vcpu *vcpu);
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#endif
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