90c5902540
All known Rockchip SoCs down to the RK28xx (ARM9) use a similar pattern to
handle their plls:
|--\
xin32k ----------------|mux\
xin24m -----| pll |----|pll|--- pll output
\---------------|src/
|--/
The pll output is sourced from 1 of 3 sources, the actual pll being one of
them. To change the pll frequency it is imperative to remux it to another
source beforehand. This is done by adding a clock-listener to the pll that
handles the remuxing before and after the rate change.
The output mux is implemented as a separate clock to make use of already
existing common-clock features for disabling the pll if one of the other
two sources is used.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-By: Max Schwarz <max.schwarz@online.de>
Tested-By: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
245 lines
6.4 KiB
C
245 lines
6.4 KiB
C
/*
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* Copyright (c) 2014 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* based on
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*
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* samsung/clk.c
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Copyright (c) 2013 Linaro Ltd.
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/slab.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "clk.h"
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/**
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* Register a clock branch.
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* Most clock branches have a form like
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*
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* src1 --|--\
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* |M |--[GATE]-[DIV]-
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* src2 --|--/
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*
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* sometimes without one of those components.
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*/
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struct clk *rockchip_clk_register_branch(const char *name,
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const char **parent_names, u8 num_parents, void __iomem *base,
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int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags,
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u8 div_shift, u8 div_width, u8 div_flags,
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struct clk_div_table *div_table, int gate_offset,
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u8 gate_shift, u8 gate_flags, unsigned long flags,
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spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_mux *mux = NULL;
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struct clk_gate *gate = NULL;
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struct clk_divider *div = NULL;
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const struct clk_ops *mux_ops = NULL, *div_ops = NULL,
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*gate_ops = NULL;
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if (num_parents > 1) {
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mux = kzalloc(sizeof(*mux), GFP_KERNEL);
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if (!mux)
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return ERR_PTR(-ENOMEM);
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mux->reg = base + muxdiv_offset;
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mux->shift = mux_shift;
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mux->mask = BIT(mux_width) - 1;
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mux->flags = mux_flags;
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mux->lock = lock;
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mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
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: &clk_mux_ops;
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}
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if (gate_offset >= 0) {
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return ERR_PTR(-ENOMEM);
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gate->flags = gate_flags;
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gate->reg = base + gate_offset;
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gate->bit_idx = gate_shift;
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gate->lock = lock;
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gate_ops = &clk_gate_ops;
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}
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if (div_width > 0) {
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div = kzalloc(sizeof(*div), GFP_KERNEL);
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if (!div)
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return ERR_PTR(-ENOMEM);
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div->flags = div_flags;
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div->reg = base + muxdiv_offset;
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div->shift = div_shift;
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div->width = div_width;
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div->lock = lock;
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div->table = div_table;
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div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
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? &clk_divider_ro_ops
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: &clk_divider_ops;
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}
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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return clk;
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}
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static DEFINE_SPINLOCK(clk_lock);
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static struct clk **clk_table;
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static void __iomem *reg_base;
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static struct clk_onecell_data clk_data;
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static struct device_node *cru_node;
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static struct regmap *grf;
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void __init rockchip_clk_init(struct device_node *np, void __iomem *base,
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unsigned long nr_clks)
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{
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reg_base = base;
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cru_node = np;
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grf = ERR_PTR(-EPROBE_DEFER);
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clk_table = kcalloc(nr_clks, sizeof(struct clk *), GFP_KERNEL);
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if (!clk_table)
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pr_err("%s: could not allocate clock lookup table\n", __func__);
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clk_data.clks = clk_table;
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clk_data.clk_num = nr_clks;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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}
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struct regmap *rockchip_clk_get_grf(void)
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{
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if (IS_ERR(grf))
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grf = syscon_regmap_lookup_by_phandle(cru_node, "rockchip,grf");
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return grf;
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}
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void rockchip_clk_add_lookup(struct clk *clk, unsigned int id)
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{
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if (clk_table && id)
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clk_table[id] = clk;
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}
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void __init rockchip_clk_register_plls(struct rockchip_pll_clock *list,
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unsigned int nr_pll, int grf_lock_offset)
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{
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struct clk *clk;
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int idx;
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for (idx = 0; idx < nr_pll; idx++, list++) {
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clk = rockchip_clk_register_pll(list->type, list->name,
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list->parent_names, list->num_parents,
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reg_base, list->con_offset, grf_lock_offset,
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list->lock_shift, list->mode_offset,
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list->mode_shift, list->rate_table, &clk_lock);
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s\n", __func__,
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list->name);
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continue;
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}
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rockchip_clk_add_lookup(clk, list->id);
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}
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}
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void __init rockchip_clk_register_branches(
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struct rockchip_clk_branch *list,
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unsigned int nr_clk)
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{
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struct clk *clk = NULL;
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unsigned int idx;
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unsigned long flags;
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for (idx = 0; idx < nr_clk; idx++, list++) {
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flags = list->flags;
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/* catch simple muxes */
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switch (list->branch_type) {
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case branch_mux:
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clk = clk_register_mux(NULL, list->name,
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list->parent_names, list->num_parents,
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flags, reg_base + list->muxdiv_offset,
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list->mux_shift, list->mux_width,
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list->mux_flags, &clk_lock);
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break;
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case branch_divider:
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if (list->div_table)
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clk = clk_register_divider_table(NULL,
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list->name, list->parent_names[0],
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flags, reg_base + list->muxdiv_offset,
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list->div_shift, list->div_width,
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list->div_flags, list->div_table,
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&clk_lock);
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else
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clk = clk_register_divider(NULL, list->name,
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list->parent_names[0], flags,
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reg_base + list->muxdiv_offset,
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list->div_shift, list->div_width,
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list->div_flags, &clk_lock);
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break;
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case branch_fraction_divider:
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/* unimplemented */
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continue;
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break;
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case branch_gate:
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flags |= CLK_SET_RATE_PARENT;
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/* keep all gates untouched for now */
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flags |= CLK_IGNORE_UNUSED;
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clk = clk_register_gate(NULL, list->name,
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list->parent_names[0], flags,
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reg_base + list->gate_offset,
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list->gate_shift, list->gate_flags, &clk_lock);
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break;
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case branch_composite:
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/* keep all gates untouched for now */
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flags |= CLK_IGNORE_UNUSED;
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clk = rockchip_clk_register_branch(list->name,
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list->parent_names, list->num_parents,
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reg_base, list->muxdiv_offset, list->mux_shift,
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list->mux_width, list->mux_flags,
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list->div_shift, list->div_width,
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list->div_flags, list->div_table,
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list->gate_offset, list->gate_shift,
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list->gate_flags, flags, &clk_lock);
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break;
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}
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/* none of the cases above matched */
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if (!clk) {
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pr_err("%s: unknown clock type %d\n",
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__func__, list->branch_type);
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continue;
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}
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if (IS_ERR(clk)) {
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pr_err("%s: failed to register clock %s: %ld\n",
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__func__, list->name, PTR_ERR(clk));
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continue;
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}
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rockchip_clk_add_lookup(clk, list->id);
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}
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}
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