10440af1bc
Now that DMA slave IDs are only used used in platform specific code and have become opaque cookies for the rest of the code, we can make the, CPU specific too. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
612 lines
15 KiB
C
612 lines
15 KiB
C
/*
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* SH7780 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/io.h>
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#include <linux/serial_sci.h>
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#include <linux/sh_dma.h>
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#include <linux/sh_timer.h>
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#include <cpu/dma-register.h>
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static struct plat_sci_port scif0_platform_data = {
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.mapbase = 0xffe00000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 40, 40, 40, 40 },
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};
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static struct platform_device scif0_device = {
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.name = "sh-sci",
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.id = 0,
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.dev = {
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.platform_data = &scif0_platform_data,
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},
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};
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static struct plat_sci_port scif1_platform_data = {
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.mapbase = 0xffe10000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 76, 76, 76, 76 },
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};
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static struct platform_device scif1_device = {
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.name = "sh-sci",
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.id = 1,
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.dev = {
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.platform_data = &scif1_platform_data,
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},
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};
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static struct sh_timer_config tmu0_platform_data = {
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.channel_offset = 0x04,
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.timer_bit = 0,
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.clockevent_rating = 200,
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};
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static struct resource tmu0_resources[] = {
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[0] = {
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.start = 0xffd80008,
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.end = 0xffd80013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 28,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu0_device = {
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.name = "sh_tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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};
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static struct sh_timer_config tmu1_platform_data = {
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clocksource_rating = 200,
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};
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static struct resource tmu1_resources[] = {
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[0] = {
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.start = 0xffd80014,
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.end = 0xffd8001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 29,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu1_device = {
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.name = "sh_tmu",
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.id = 1,
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.dev = {
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.platform_data = &tmu1_platform_data,
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},
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.resource = tmu1_resources,
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.num_resources = ARRAY_SIZE(tmu1_resources),
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};
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static struct sh_timer_config tmu2_platform_data = {
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.channel_offset = 0x1c,
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.timer_bit = 2,
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};
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static struct resource tmu2_resources[] = {
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[0] = {
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.start = 0xffd80020,
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.end = 0xffd8002f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 30,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu2_device = {
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.name = "sh_tmu",
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.id = 2,
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.dev = {
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.platform_data = &tmu2_platform_data,
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},
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.resource = tmu2_resources,
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.num_resources = ARRAY_SIZE(tmu2_resources),
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};
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static struct sh_timer_config tmu3_platform_data = {
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.channel_offset = 0x04,
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.timer_bit = 0,
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};
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static struct resource tmu3_resources[] = {
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[0] = {
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.start = 0xffdc0008,
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.end = 0xffdc0013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 96,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu3_device = {
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.name = "sh_tmu",
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.id = 3,
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.dev = {
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.platform_data = &tmu3_platform_data,
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},
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.resource = tmu3_resources,
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.num_resources = ARRAY_SIZE(tmu3_resources),
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};
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static struct sh_timer_config tmu4_platform_data = {
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.channel_offset = 0x10,
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.timer_bit = 1,
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};
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static struct resource tmu4_resources[] = {
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[0] = {
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.start = 0xffdc0014,
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.end = 0xffdc001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 97,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu4_device = {
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.name = "sh_tmu",
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.id = 4,
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.dev = {
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.platform_data = &tmu4_platform_data,
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},
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.resource = tmu4_resources,
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.num_resources = ARRAY_SIZE(tmu4_resources),
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};
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static struct sh_timer_config tmu5_platform_data = {
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.channel_offset = 0x1c,
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.timer_bit = 2,
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};
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static struct resource tmu5_resources[] = {
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[0] = {
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.start = 0xffdc0020,
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.end = 0xffdc002b,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 98,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu5_device = {
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.name = "sh_tmu",
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.id = 5,
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.dev = {
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.platform_data = &tmu5_platform_data,
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},
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.resource = tmu5_resources,
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.num_resources = ARRAY_SIZE(tmu5_resources),
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};
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xffe80000,
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.end = 0xffe80000 + 0x58 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Shared Period/Carry/Alarm IRQ */
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.start = 20,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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/* DMA */
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static const struct sh_dmae_channel sh7780_dmae0_channels[] = {
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{
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.offset = 0,
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.dmars = 0,
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.dmars_bit = 0,
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}, {
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.offset = 0x10,
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.dmars = 0,
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.dmars_bit = 8,
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}, {
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.offset = 0x20,
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.dmars = 4,
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.dmars_bit = 0,
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}, {
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.offset = 0x30,
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.dmars = 4,
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.dmars_bit = 8,
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}, {
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.offset = 0x50,
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.dmars = 8,
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.dmars_bit = 0,
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}, {
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.offset = 0x60,
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.dmars = 8,
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.dmars_bit = 8,
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}
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};
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static const struct sh_dmae_channel sh7780_dmae1_channels[] = {
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{
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.offset = 0,
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}, {
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.offset = 0x10,
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}, {
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.offset = 0x20,
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}, {
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.offset = 0x30,
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}, {
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.offset = 0x50,
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}, {
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.offset = 0x60,
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}
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};
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static const unsigned int ts_shift[] = TS_SHIFT;
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static struct sh_dmae_pdata dma0_platform_data = {
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.channel = sh7780_dmae0_channels,
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.channel_num = ARRAY_SIZE(sh7780_dmae0_channels),
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.ts_low_shift = CHCR_TS_LOW_SHIFT,
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.ts_low_mask = CHCR_TS_LOW_MASK,
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.ts_high_shift = CHCR_TS_HIGH_SHIFT,
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.ts_high_mask = CHCR_TS_HIGH_MASK,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_INIT,
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};
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static struct sh_dmae_pdata dma1_platform_data = {
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.channel = sh7780_dmae1_channels,
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.channel_num = ARRAY_SIZE(sh7780_dmae1_channels),
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.ts_low_shift = CHCR_TS_LOW_SHIFT,
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.ts_low_mask = CHCR_TS_LOW_MASK,
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.ts_high_shift = CHCR_TS_HIGH_SHIFT,
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.ts_high_mask = CHCR_TS_HIGH_MASK,
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.ts_shift = ts_shift,
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.ts_shift_num = ARRAY_SIZE(ts_shift),
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.dmaor_init = DMAOR_INIT,
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};
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static struct resource sh7780_dmae0_resources[] = {
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[0] = {
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/* Channel registers and DMAOR */
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.start = 0xfc808020,
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.end = 0xfc80808f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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/* DMARSx */
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.start = 0xfc809000,
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.end = 0xfc80900b,
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.flags = IORESOURCE_MEM,
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},
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{
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/* Real DMA error IRQ is 38, and channel IRQs are 34-37, 44-45 */
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.start = 34,
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.end = 34,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
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},
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};
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static struct resource sh7780_dmae1_resources[] = {
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[0] = {
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/* Channel registers and DMAOR */
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.start = 0xfc818020,
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.end = 0xfc81808f,
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.flags = IORESOURCE_MEM,
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},
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/* DMAC1 has no DMARS */
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{
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/* Real DMA error IRQ is 38, and channel IRQs are 46-47, 92-95 */
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.start = 46,
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.end = 46,
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.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_SHAREABLE,
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},
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};
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static struct platform_device dma0_device = {
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.name = "sh-dma-engine",
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.id = 0,
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.resource = sh7780_dmae0_resources,
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.num_resources = ARRAY_SIZE(sh7780_dmae0_resources),
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.dev = {
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.platform_data = &dma0_platform_data,
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},
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};
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static struct platform_device dma1_device = {
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.name = "sh-dma-engine",
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.id = 1,
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.resource = sh7780_dmae1_resources,
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.num_resources = ARRAY_SIZE(sh7780_dmae1_resources),
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.dev = {
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.platform_data = &dma1_platform_data,
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},
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};
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static struct platform_device *sh7780_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&tmu0_device,
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&tmu1_device,
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&tmu2_device,
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&tmu3_device,
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&tmu4_device,
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&tmu5_device,
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&rtc_device,
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&dma0_device,
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&dma1_device,
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};
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static int __init sh7780_devices_setup(void)
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{
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return platform_add_devices(sh7780_devices,
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ARRAY_SIZE(sh7780_devices));
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}
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arch_initcall(sh7780_devices_setup);
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static struct platform_device *sh7780_early_devices[] __initdata = {
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&scif0_device,
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&scif1_device,
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&tmu0_device,
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&tmu1_device,
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&tmu2_device,
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&tmu3_device,
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&tmu4_device,
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&tmu5_device,
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};
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void __init plat_early_device_setup(void)
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{
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early_platform_add_devices(sh7780_early_devices,
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ARRAY_SIZE(sh7780_early_devices));
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}
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
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IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
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IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
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IRL_HHLL, IRL_HHLH, IRL_HHHL,
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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RTC, WDT, TMU0, TMU1, TMU2, TMU2_TICPI,
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HUDI, DMAC0, SCIF0, DMAC1, CMT, HAC,
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PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, PCIC5,
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SCIF1, SIOF, HSPI, MMCIF, TMU3, TMU4, TMU5, SSI, FLCTL, GPIO,
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/* interrupt groups */
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TMU012, TMU345,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
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INTC_VECT(RTC, 0x4c0),
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INTC_VECT(WDT, 0x560),
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INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
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INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
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INTC_VECT(HUDI, 0x600),
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INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
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INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
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INTC_VECT(DMAC0, 0x6c0),
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INTC_VECT(SCIF0, 0x700), INTC_VECT(SCIF0, 0x720),
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INTC_VECT(SCIF0, 0x740), INTC_VECT(SCIF0, 0x760),
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INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
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INTC_VECT(DMAC1, 0x7c0), INTC_VECT(DMAC1, 0x7e0),
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INTC_VECT(CMT, 0x900), INTC_VECT(HAC, 0x980),
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INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20),
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INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60),
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INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIC5, 0xaa0),
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INTC_VECT(PCIC5, 0xac0), INTC_VECT(PCIC5, 0xae0),
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INTC_VECT(PCIC5, 0xb00), INTC_VECT(PCIC5, 0xb20),
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INTC_VECT(SCIF1, 0xb80), INTC_VECT(SCIF1, 0xba0),
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INTC_VECT(SCIF1, 0xbc0), INTC_VECT(SCIF1, 0xbe0),
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INTC_VECT(SIOF, 0xc00), INTC_VECT(HSPI, 0xc80),
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INTC_VECT(MMCIF, 0xd00), INTC_VECT(MMCIF, 0xd20),
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INTC_VECT(MMCIF, 0xd40), INTC_VECT(MMCIF, 0xd60),
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INTC_VECT(DMAC1, 0xd80), INTC_VECT(DMAC1, 0xda0),
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INTC_VECT(DMAC1, 0xdc0), INTC_VECT(DMAC1, 0xde0),
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INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
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INTC_VECT(TMU5, 0xe40),
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INTC_VECT(SSI, 0xe80),
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INTC_VECT(FLCTL, 0xf00), INTC_VECT(FLCTL, 0xf20),
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INTC_VECT(FLCTL, 0xf40), INTC_VECT(FLCTL, 0xf60),
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INTC_VECT(GPIO, 0xf80), INTC_VECT(GPIO, 0xfa0),
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INTC_VECT(GPIO, 0xfc0), INTC_VECT(GPIO, 0xfe0),
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
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INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
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{ 0, 0, 0, 0, 0, 0, GPIO, FLCTL,
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SSI, MMCIF, HSPI, SIOF, PCIC5, PCIINTD, PCIINTC, PCIINTB,
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PCIINTA, PCISERR, HAC, CMT, 0, 0, DMAC1, DMAC0,
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HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } },
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1,
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TMU2, TMU2_TICPI } },
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{ 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } },
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{ 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } },
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{ 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC0, DMAC1 } },
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{ 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC,
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PCISERR, PCIINTA, } },
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{ 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC,
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PCIINTD, PCIC5 } },
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|
{ 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF, HSPI, MMCIF, SSI } },
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|
{ 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL, GPIO } },
|
|
};
|
|
|
|
static DECLARE_INTC_DESC(intc_desc, "sh7780", vectors, groups,
|
|
mask_registers, prio_registers, NULL);
|
|
|
|
/* Support for external interrupt pins in IRQ mode */
|
|
|
|
static struct intc_vect irq_vectors[] __initdata = {
|
|
INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
|
|
INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
|
|
INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
|
|
INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
|
|
};
|
|
|
|
static struct intc_mask_reg irq_mask_registers[] __initdata = {
|
|
{ 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
|
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
|
};
|
|
|
|
static struct intc_prio_reg irq_prio_registers[] __initdata = {
|
|
{ 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
|
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
|
};
|
|
|
|
static struct intc_sense_reg irq_sense_registers[] __initdata = {
|
|
{ 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
|
|
IRQ4, IRQ5, IRQ6, IRQ7 } },
|
|
};
|
|
|
|
static struct intc_mask_reg irq_ack_registers[] __initdata = {
|
|
{ 0xffd00024, 0, 32, /* INTREQ */
|
|
{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
|
|
};
|
|
|
|
static DECLARE_INTC_DESC_ACK(intc_irq_desc, "sh7780-irq", irq_vectors,
|
|
NULL, irq_mask_registers, irq_prio_registers,
|
|
irq_sense_registers, irq_ack_registers);
|
|
|
|
/* External interrupt pins in IRL mode */
|
|
|
|
static struct intc_vect irl_vectors[] __initdata = {
|
|
INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
|
|
INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
|
|
INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
|
|
INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
|
|
INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
|
|
INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
|
|
INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
|
|
INTC_VECT(IRL_HHHL, 0x3c0),
|
|
};
|
|
|
|
static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
|
|
{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
|
|
{ IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
|
|
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
|
|
IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
|
|
IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
|
|
};
|
|
|
|
static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
|
|
{ 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
|
|
IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
|
|
IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
|
|
IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
|
|
IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
|
|
};
|
|
|
|
static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
|
|
NULL, irl7654_mask_registers, NULL, NULL);
|
|
|
|
static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
|
|
NULL, irl3210_mask_registers, NULL, NULL);
|
|
|
|
#define INTC_ICR0 0xffd00000
|
|
#define INTC_INTMSK0 0xffd00044
|
|
#define INTC_INTMSK1 0xffd00048
|
|
#define INTC_INTMSK2 0xffd40080
|
|
#define INTC_INTMSKCLR1 0xffd00068
|
|
#define INTC_INTMSKCLR2 0xffd40084
|
|
|
|
void __init plat_irq_setup(void)
|
|
{
|
|
/* disable IRQ7-0 */
|
|
__raw_writel(0xff000000, INTC_INTMSK0);
|
|
|
|
/* disable IRL3-0 + IRL7-4 */
|
|
__raw_writel(0xc0000000, INTC_INTMSK1);
|
|
__raw_writel(0xfffefffe, INTC_INTMSK2);
|
|
|
|
/* select IRL mode for IRL3-0 + IRL7-4 */
|
|
__raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
|
|
|
|
/* disable holding function, ie enable "SH-4 Mode" */
|
|
__raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
|
|
|
|
register_intc_controller(&intc_desc);
|
|
}
|
|
|
|
void __init plat_irq_setup_pins(int mode)
|
|
{
|
|
switch (mode) {
|
|
case IRQ_MODE_IRQ:
|
|
/* select IRQ mode for IRL3-0 + IRL7-4 */
|
|
__raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
|
|
register_intc_controller(&intc_irq_desc);
|
|
break;
|
|
case IRQ_MODE_IRL7654:
|
|
/* enable IRL7-4 but don't provide any masking */
|
|
__raw_writel(0x40000000, INTC_INTMSKCLR1);
|
|
__raw_writel(0x0000fffe, INTC_INTMSKCLR2);
|
|
break;
|
|
case IRQ_MODE_IRL3210:
|
|
/* enable IRL0-3 but don't provide any masking */
|
|
__raw_writel(0x80000000, INTC_INTMSKCLR1);
|
|
__raw_writel(0xfffe0000, INTC_INTMSKCLR2);
|
|
break;
|
|
case IRQ_MODE_IRL7654_MASK:
|
|
/* enable IRL7-4 and mask using cpu intc controller */
|
|
__raw_writel(0x40000000, INTC_INTMSKCLR1);
|
|
register_intc_controller(&intc_irl7654_desc);
|
|
break;
|
|
case IRQ_MODE_IRL3210_MASK:
|
|
/* enable IRL0-3 and mask using cpu intc controller */
|
|
__raw_writel(0x80000000, INTC_INTMSKCLR1);
|
|
register_intc_controller(&intc_irl3210_desc);
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
}
|