a61ea9326d
Patch from Nicolas Pitre This field is redundent since it must be equal to PHYS_OFFSET anyway. There is no reference to it anymore so remove it at last. Signed-off-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
530 lines
14 KiB
ArmAsm
530 lines
14 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Kernel startup code for all 32-bit CPUs
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*/
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/domain.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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#include <asm/asm-offsets.h>
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#include <asm/memory.h>
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#include <asm/thread_info.h>
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#include <asm/system.h>
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#define PROCINFO_MMUFLAGS 8
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#define PROCINFO_INITFUNC 12
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#define MACHINFO_TYPE 0
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#define MACHINFO_PHYSIO 4
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#define MACHINFO_PGOFFIO 8
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#define MACHINFO_NAME 12
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#define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET)
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/*
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* swapper_pg_dir is the virtual address of the initial page table.
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* We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must
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* make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect
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* the least significant 16 bits to be 0x8000, but we could probably
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* relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000.
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*/
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#if (KERNEL_RAM_ADDR & 0xffff) != 0x8000
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#error KERNEL_RAM_ADDR must start at 0xXXXX8000
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000
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.macro pgtbl, rd
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ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000))
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.endm
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#ifdef CONFIG_XIP_KERNEL
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#define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
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#else
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#define TEXTADDR KERNEL_RAM_ADDR
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#endif
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* This is normally called from the decompressor code. The requirements
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* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
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* r1 = machine nr.
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*
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* This code is mostly position independent, so if you link the kernel at
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* 0xc0008000, you call this at __pa(0xc0008000).
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*
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* See linux/arch/arm/tools/mach-types for the complete list of machine
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* numbers for r1.
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*
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* We're trying to keep crap to a minimum; DO NOT add any machine specific
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* crap here - that's what the boot loader (or in extreme, well justified
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* circumstances, zImage) is for.
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*/
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__INIT
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.type stext, %function
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ENTRY(stext)
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
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@ and irqs disabled
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bl __lookup_processor_type @ r5=procinfo r9=cpuid
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movs r10, r5 @ invalid processor (r5=0)?
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beq __error_p @ yes, error 'p'
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bl __lookup_machine_type @ r5=machinfo
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movs r8, r5 @ invalid machine (r5=0)?
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beq __error_a @ yes, error 'a'
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bl __create_page_tables
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/*
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* The following calls CPU specific code in a position independent
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* manner. See arch/arm/mm/proc-*.S for details. r10 = base of
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* xxx_proc_info structure selected by __lookup_machine_type
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* above. On return, the CPU will be ready for the MMU to be
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* turned on, and r0 will hold the CPU control register value.
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*/
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ldr r13, __switch_data @ address to jump to after
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@ mmu has been enabled
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adr lr, __enable_mmu @ return (PIC) address
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add pc, r10, #PROCINFO_INITFUNC
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.type __switch_data, %object
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__switch_data:
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.long __mmap_switched
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.long __data_loc @ r4
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.long __data_start @ r5
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.long __bss_start @ r6
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.long _end @ r7
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.long processor_id @ r4
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.long __machine_arch_type @ r5
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.long cr_alignment @ r6
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.long init_thread_union + THREAD_START_SP @ sp
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/*
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* The following fragment of code is executed with the MMU on, and uses
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* absolute addresses; this is not position independent.
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*
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* r0 = cp#15 control register
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* r1 = machine ID
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* r9 = processor ID
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*/
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.type __mmap_switched, %function
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__mmap_switched:
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adr r3, __switch_data + 4
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ldmia r3!, {r4, r5, r6, r7}
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cmp r4, r5 @ Copy data segment if needed
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1: cmpne r5, r6
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ldrne fp, [r4], #4
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strne fp, [r5], #4
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bne 1b
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mov fp, #0 @ Clear BSS (and zero fp)
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1: cmp r6, r7
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strcc fp, [r6],#4
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bcc 1b
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ldmia r3, {r4, r5, r6, sp}
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str r9, [r4] @ Save processor ID
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str r1, [r5] @ Save machine type
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bic r4, r0, #CR_A @ Clear 'A' bit
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stmia r6, {r0, r4} @ Save control register values
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b start_kernel
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#if defined(CONFIG_SMP)
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.type secondary_startup, #function
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ENTRY(secondary_startup)
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/*
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* Common entry point for secondary CPUs.
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*
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* Ensure that we're in SVC mode, and IRQs are disabled. Lookup
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* the processor type - there is no need to check the machine type
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* as it has already been validated by the primary processor.
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*/
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msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
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bl __lookup_processor_type
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movs r10, r5 @ invalid processor?
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moveq r0, #'p' @ yes, error 'p'
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beq __error
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/*
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* Use the page tables supplied from __cpu_up.
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*/
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adr r4, __secondary_data
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ldmia r4, {r5, r6, r13} @ address to jump to after
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sub r4, r4, r5 @ mmu has been enabled
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ldr r4, [r6, r4] @ get secondary_data.pgdir
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adr lr, __enable_mmu @ return address
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add pc, r10, #12 @ initialise processor
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@ (return control reg)
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/*
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* r6 = &secondary_data
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*/
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ENTRY(__secondary_switched)
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ldr sp, [r6, #4] @ get secondary_data.stack
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mov fp, #0
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b secondary_start_kernel
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.type __secondary_data, %object
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__secondary_data:
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.long .
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.long secondary_data
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.long __secondary_switched
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#endif /* defined(CONFIG_SMP) */
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/*
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* Setup common bits before finally enabling the MMU. Essentially
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* this is just loading the page table pointer and domain access
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* registers.
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*/
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.type __enable_mmu, %function
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__enable_mmu:
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#ifdef CONFIG_ALIGNMENT_TRAP
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orr r0, r0, #CR_A
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#else
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bic r0, r0, #CR_A
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#endif
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#ifdef CONFIG_CPU_DCACHE_DISABLE
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bic r0, r0, #CR_C
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#endif
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#ifdef CONFIG_CPU_BPREDICT_DISABLE
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bic r0, r0, #CR_Z
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#endif
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#ifdef CONFIG_CPU_ICACHE_DISABLE
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bic r0, r0, #CR_I
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#endif
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mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
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domain_val(DOMAIN_IO, DOMAIN_CLIENT))
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mcr p15, 0, r5, c3, c0, 0 @ load domain access register
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mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
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b __turn_mmu_on
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/*
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* Enable the MMU. This completely changes the structure of the visible
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* memory space. You will not be able to trace execution through this.
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* If you have an enquiry about this, *please* check the linux-arm-kernel
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* mailing list archives BEFORE sending another post to the list.
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*
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* r0 = cp#15 control register
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* r13 = *virtual* address to jump to upon completion
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*
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* other registers depend on the function called upon completion
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*/
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.align 5
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.type __turn_mmu_on, %function
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__turn_mmu_on:
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mov r0, r0
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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mrc p15, 0, r3, c0, c0, 0 @ read id reg
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mov r3, r3
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mov r3, r3
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mov pc, r13
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/*
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* Setup the initial page tables. We only setup the barest
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* amount which are required to get the kernel running, which
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* generally means mapping in the kernel code.
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*
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* r8 = machinfo
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* r9 = cpuid
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* r10 = procinfo
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*
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* Returns:
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* r0, r3, r6, r7 corrupted
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* r4 = physical page table address
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*/
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.type __create_page_tables, %function
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__create_page_tables:
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pgtbl r4 @ page table address
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/*
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* Clear the 16K level 1 swapper page table
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*/
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mov r0, r4
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mov r3, #0
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add r6, r0, #0x4000
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1: str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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teq r0, r6
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bne 1b
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ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags
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/*
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* Create identity mapping for first MB of kernel to
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* cater for the MMU enable. This identity mapping
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* will be removed by paging_init(). We use our current program
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* counter to determine corresponding section base address.
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*/
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mov r6, pc, lsr #20 @ start of kernel section
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orr r3, r7, r6, lsl #20 @ flags + kernel base
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str r3, [r4, r6, lsl #2] @ identity mapping
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/*
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* Now setup the pagetables for our kernel direct
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* mapped region. We round TEXTADDR down to the
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* nearest megabyte boundary. It is assumed that
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* the kernel fits within 4 contigous 1MB sections.
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*/
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add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
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str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
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add r3, r3, #1 << 20
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str r3, [r0, #4]! @ KERNEL + 1MB
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add r3, r3, #1 << 20
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str r3, [r0, #4]! @ KERNEL + 2MB
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add r3, r3, #1 << 20
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str r3, [r0, #4] @ KERNEL + 3MB
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/*
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* Then map first 1MB of ram in case it contains our boot params.
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*/
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add r0, r4, #PAGE_OFFSET >> 18
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orr r6, r7, #PHYS_OFFSET
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str r6, [r0]
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#ifdef CONFIG_XIP_KERNEL
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/*
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* Map some ram to cover our .data and .bss areas.
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* Mapping 3MB should be plenty.
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*/
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sub r3, r4, #PHYS_OFFSET
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mov r3, r3, lsr #20
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add r0, r0, r3, lsl #2
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add r6, r6, r3, lsl #20
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str r6, [r0], #4
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add r6, r6, #(1 << 20)
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str r6, [r0], #4
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add r6, r6, #(1 << 20)
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str r6, [r0]
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#endif
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#ifdef CONFIG_DEBUG_LL
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bic r7, r7, #0x0c @ turn off cacheable
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@ and bufferable bits
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/*
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* Map in IO space for serial debugging.
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* This allows debug messages to be output
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* via a serial console before paging_init.
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*/
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ldr r3, [r8, #MACHINFO_PGOFFIO]
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add r0, r4, r3
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rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
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cmp r3, #0x0800 @ limit to 512MB
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movhi r3, #0x0800
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add r6, r0, r3
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ldr r3, [r8, #MACHINFO_PHYSIO]
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orr r3, r3, r7
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1: str r3, [r0], #4
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add r3, r3, #1 << 20
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teq r0, r6
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bne 1b
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#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
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/*
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* If we're using the NetWinder or CATS, we also need to map
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* in the 16550-type serial port for the debug messages
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*/
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add r0, r4, #0xff000000 >> 18
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orr r3, r7, #0x7c000000
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str r3, [r0]
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#endif
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#ifdef CONFIG_ARCH_RPC
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/*
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* Map in screen at 0x02000000 & SCREEN2_BASE
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* Similar reasons here - for debug. This is
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* only for Acorn RiscPC architectures.
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*/
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add r0, r4, #0x02000000 >> 18
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orr r3, r7, #0x02000000
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str r3, [r0]
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add r0, r4, #0xd8000000 >> 18
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str r3, [r0]
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#endif
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#endif
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mov pc, lr
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.ltorg
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/*
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* Exception handling. Something went wrong and we can't proceed. We
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* ought to tell the user, but since we don't have any guarantee that
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* we're even running on the right architecture, we do virtually nothing.
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*
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* If CONFIG_DEBUG_LL is set we try to print out something about the error
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* and hope for the best (useful if bootloader fails to pass a proper
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* machine ID for example).
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*/
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.type __error_p, %function
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__error_p:
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#ifdef CONFIG_DEBUG_LL
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adr r0, str_p1
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bl printascii
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b __error
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str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n"
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.align
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#endif
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.type __error_a, %function
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__error_a:
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#ifdef CONFIG_DEBUG_LL
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mov r4, r1 @ preserve machine ID
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adr r0, str_a1
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bl printascii
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mov r0, r4
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bl printhex8
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adr r0, str_a2
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bl printascii
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adr r3, 3f
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ldmia r3, {r4, r5, r6} @ get machine desc list
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sub r4, r3, r4 @ get offset between virt&phys
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add r5, r5, r4 @ convert virt addresses to
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add r6, r6, r4 @ physical address space
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1: ldr r0, [r5, #MACHINFO_TYPE] @ get machine type
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bl printhex8
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mov r0, #'\t'
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bl printch
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ldr r0, [r5, #MACHINFO_NAME] @ get machine name
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add r0, r0, r4
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bl printascii
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mov r0, #'\n'
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bl printch
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add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
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cmp r5, r6
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blo 1b
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adr r0, str_a3
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bl printascii
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b __error
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str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x"
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str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n"
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str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n"
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.align
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#endif
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.type __error, %function
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__error:
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#ifdef CONFIG_ARCH_RPC
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/*
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* Turn the screen red on a error - RiscPC only.
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*/
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mov r0, #0x02000000
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mov r3, #0x11
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orr r3, r3, r3, lsl #8
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orr r3, r3, r3, lsl #16
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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#endif
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1: mov r0, r0
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b 1b
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/*
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* Read processor ID register (CP#15, CR0), and look up in the linker-built
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* supported processor list. Note that we can't use the absolute addresses
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* for the __proc_info lists since we aren't running with the MMU on
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* (and therefore, we are not in the correct address space). We have to
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* calculate the offset.
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*
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* Returns:
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* r3, r4, r6 corrupted
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* r5 = proc_info pointer in physical address space
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* r9 = cpuid
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*/
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.type __lookup_processor_type, %function
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__lookup_processor_type:
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adr r3, 3f
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ldmda r3, {r5, r6, r9}
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sub r3, r3, r9 @ get offset between virt&phys
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add r5, r5, r3 @ convert virt addresses to
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add r6, r6, r3 @ physical address space
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mrc p15, 0, r9, c0, c0 @ get processor id
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1: ldmia r5, {r3, r4} @ value, mask
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and r4, r4, r9 @ mask wanted bits
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teq r3, r4
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beq 2f
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add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
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cmp r5, r6
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blo 1b
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mov r5, #0 @ unknown processor
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2: mov pc, lr
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/*
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* This provides a C-API version of the above function.
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*/
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ENTRY(lookup_processor_type)
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stmfd sp!, {r4 - r6, r9, lr}
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bl __lookup_processor_type
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mov r0, r5
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ldmfd sp!, {r4 - r6, r9, pc}
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/*
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* Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
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* more information about the __proc_info and __arch_info structures.
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*/
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.long __proc_info_begin
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.long __proc_info_end
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3: .long .
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.long __arch_info_begin
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.long __arch_info_end
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/*
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* Lookup machine architecture in the linker-build list of architectures.
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* Note that we can't use the absolute addresses for the __arch_info
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* lists since we aren't running with the MMU on (and therefore, we are
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* not in the correct address space). We have to calculate the offset.
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*
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* r1 = machine architecture number
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* Returns:
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* r3, r4, r6 corrupted
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* r5 = mach_info pointer in physical address space
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*/
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.type __lookup_machine_type, %function
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__lookup_machine_type:
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adr r3, 3b
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ldmia r3, {r4, r5, r6}
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sub r3, r3, r4 @ get offset between virt&phys
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add r5, r5, r3 @ convert virt addresses to
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add r6, r6, r3 @ physical address space
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1: ldr r3, [r5, #MACHINFO_TYPE] @ get machine type
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teq r3, r1 @ matches loader number?
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beq 2f @ found
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add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc
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cmp r5, r6
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blo 1b
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mov r5, #0 @ unknown machine
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2: mov pc, lr
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/*
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* This provides a C-API version of the above function.
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*/
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ENTRY(lookup_machine_type)
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stmfd sp!, {r4 - r6, lr}
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mov r1, r0
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bl __lookup_machine_type
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mov r0, r5
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ldmfd sp!, {r4 - r6, pc}
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