342 lines
7.3 KiB
C
342 lines
7.3 KiB
C
/*
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* linux/arch/arm/mach-rpc/dma.c
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*
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* Copyright (C) 1998 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* DMA functions specific to RiscPC architecture
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*/
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#include <linux/slab.h>
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#include <linux/mman.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <asm/page.h>
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#include <asm/dma.h>
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#include <asm/fiq.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <asm/uaccess.h>
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#include <asm/mach/dma.h>
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#include <asm/hardware/iomd.h>
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#if 0
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typedef enum {
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dma_size_8 = 1,
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dma_size_16 = 2,
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dma_size_32 = 4,
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dma_size_128 = 16
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} dma_size_t;
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#endif
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#define TRANSFER_SIZE 2
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#define CURA (0)
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#define ENDA (IOMD_IO0ENDA - IOMD_IO0CURA)
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#define CURB (IOMD_IO0CURB - IOMD_IO0CURA)
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#define ENDB (IOMD_IO0ENDB - IOMD_IO0CURA)
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#define CR (IOMD_IO0CR - IOMD_IO0CURA)
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#define ST (IOMD_IO0ST - IOMD_IO0CURA)
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static void iomd_get_next_sg(struct scatterlist *sg, dma_t *dma)
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{
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unsigned long end, offset, flags = 0;
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if (dma->sg) {
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sg->dma_address = dma->sg->dma_address;
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offset = sg->dma_address & ~PAGE_MASK;
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end = offset + dma->sg->length;
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if (end > PAGE_SIZE)
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end = PAGE_SIZE;
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if (offset + TRANSFER_SIZE >= end)
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flags |= DMA_END_L;
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sg->length = end - TRANSFER_SIZE;
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dma->sg->length -= end - offset;
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dma->sg->dma_address += end - offset;
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if (dma->sg->length == 0) {
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if (dma->sgcount > 1) {
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dma->sg++;
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dma->sgcount--;
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} else {
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dma->sg = NULL;
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flags |= DMA_END_S;
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}
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}
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} else {
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flags = DMA_END_S | DMA_END_L;
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sg->dma_address = 0;
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sg->length = 0;
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}
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sg->length |= flags;
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}
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static irqreturn_t iomd_dma_handle(int irq, void *dev_id)
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{
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dma_t *dma = (dma_t *)dev_id;
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unsigned long base = dma->dma_base;
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do {
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unsigned int status;
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status = iomd_readb(base + ST);
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if (!(status & DMA_ST_INT))
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return IRQ_HANDLED;
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if ((dma->state ^ status) & DMA_ST_AB)
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iomd_get_next_sg(&dma->cur_sg, dma);
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switch (status & (DMA_ST_OFL | DMA_ST_AB)) {
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case DMA_ST_OFL: /* OIA */
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case DMA_ST_AB: /* .IB */
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iomd_writel(dma->cur_sg.dma_address, base + CURA);
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iomd_writel(dma->cur_sg.length, base + ENDA);
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dma->state = DMA_ST_AB;
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break;
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case DMA_ST_OFL | DMA_ST_AB: /* OIB */
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case 0: /* .IA */
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iomd_writel(dma->cur_sg.dma_address, base + CURB);
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iomd_writel(dma->cur_sg.length, base + ENDB);
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dma->state = 0;
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break;
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}
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if (status & DMA_ST_OFL &&
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dma->cur_sg.length == (DMA_END_S|DMA_END_L))
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break;
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} while (1);
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dma->state = ~DMA_ST_AB;
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disable_irq(irq);
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return IRQ_HANDLED;
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}
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static int iomd_request_dma(dmach_t channel, dma_t *dma)
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{
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return request_irq(dma->dma_irq, iomd_dma_handle,
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IRQF_DISABLED, dma->device_id, dma);
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}
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static void iomd_free_dma(dmach_t channel, dma_t *dma)
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{
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free_irq(dma->dma_irq, dma);
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}
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static void iomd_enable_dma(dmach_t channel, dma_t *dma)
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{
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unsigned long dma_base = dma->dma_base;
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unsigned int ctrl = TRANSFER_SIZE | DMA_CR_E;
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if (dma->invalid) {
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dma->invalid = 0;
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/*
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* Cope with ISA-style drivers which expect cache
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* coherence.
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*/
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if (!dma->sg) {
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dma->sg = &dma->buf;
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dma->sgcount = 1;
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dma->buf.length = dma->count;
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dma->buf.dma_address = dma_map_single(NULL,
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dma->addr, dma->count,
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dma->dma_mode == DMA_MODE_READ ?
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DMA_FROM_DEVICE : DMA_TO_DEVICE);
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}
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iomd_writeb(DMA_CR_C, dma_base + CR);
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dma->state = DMA_ST_AB;
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}
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if (dma->dma_mode == DMA_MODE_READ)
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ctrl |= DMA_CR_D;
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iomd_writeb(ctrl, dma_base + CR);
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enable_irq(dma->dma_irq);
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}
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static void iomd_disable_dma(dmach_t channel, dma_t *dma)
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{
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unsigned long dma_base = dma->dma_base;
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unsigned long flags;
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local_irq_save(flags);
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if (dma->state != ~DMA_ST_AB)
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disable_irq(dma->dma_irq);
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iomd_writeb(0, dma_base + CR);
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local_irq_restore(flags);
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}
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static int iomd_set_dma_speed(dmach_t channel, dma_t *dma, int cycle)
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{
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int tcr, speed;
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if (cycle < 188)
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speed = 3;
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else if (cycle <= 250)
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speed = 2;
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else if (cycle < 438)
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speed = 1;
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else
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speed = 0;
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tcr = iomd_readb(IOMD_DMATCR);
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speed &= 3;
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switch (channel) {
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case DMA_0:
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tcr = (tcr & ~0x03) | speed;
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break;
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case DMA_1:
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tcr = (tcr & ~0x0c) | (speed << 2);
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break;
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case DMA_2:
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tcr = (tcr & ~0x30) | (speed << 4);
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break;
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case DMA_3:
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tcr = (tcr & ~0xc0) | (speed << 6);
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break;
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default:
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break;
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}
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iomd_writeb(tcr, IOMD_DMATCR);
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return speed;
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}
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static struct dma_ops iomd_dma_ops = {
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.type = "IOMD",
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.request = iomd_request_dma,
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.free = iomd_free_dma,
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.enable = iomd_enable_dma,
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.disable = iomd_disable_dma,
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.setspeed = iomd_set_dma_speed,
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};
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static struct fiq_handler fh = {
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.name = "floppydma"
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};
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static void floppy_enable_dma(dmach_t channel, dma_t *dma)
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{
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void *fiqhandler_start;
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unsigned int fiqhandler_length;
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struct pt_regs regs;
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if (dma->sg)
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BUG();
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if (dma->dma_mode == DMA_MODE_READ) {
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extern unsigned char floppy_fiqin_start, floppy_fiqin_end;
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fiqhandler_start = &floppy_fiqin_start;
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fiqhandler_length = &floppy_fiqin_end - &floppy_fiqin_start;
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} else {
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extern unsigned char floppy_fiqout_start, floppy_fiqout_end;
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fiqhandler_start = &floppy_fiqout_start;
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fiqhandler_length = &floppy_fiqout_end - &floppy_fiqout_start;
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}
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regs.ARM_r9 = dma->count;
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regs.ARM_r10 = (unsigned long)dma->addr;
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regs.ARM_fp = (unsigned long)FLOPPYDMA_BASE;
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if (claim_fiq(&fh)) {
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printk("floppydma: couldn't claim FIQ.\n");
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return;
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}
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set_fiq_handler(fiqhandler_start, fiqhandler_length);
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set_fiq_regs(®s);
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enable_fiq(dma->dma_irq);
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}
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static void floppy_disable_dma(dmach_t channel, dma_t *dma)
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{
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disable_fiq(dma->dma_irq);
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release_fiq(&fh);
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}
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static int floppy_get_residue(dmach_t channel, dma_t *dma)
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{
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struct pt_regs regs;
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get_fiq_regs(®s);
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return regs.ARM_r9;
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}
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static struct dma_ops floppy_dma_ops = {
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.type = "FIQDMA",
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.enable = floppy_enable_dma,
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.disable = floppy_disable_dma,
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.residue = floppy_get_residue,
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};
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/*
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* This is virtual DMA - we don't need anything here.
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*/
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static void sound_enable_disable_dma(dmach_t channel, dma_t *dma)
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{
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}
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static struct dma_ops sound_dma_ops = {
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.type = "VIRTUAL",
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.enable = sound_enable_disable_dma,
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.disable = sound_enable_disable_dma,
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};
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void __init arch_dma_init(dma_t *dma)
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{
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iomd_writeb(0, IOMD_IO0CR);
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iomd_writeb(0, IOMD_IO1CR);
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iomd_writeb(0, IOMD_IO2CR);
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iomd_writeb(0, IOMD_IO3CR);
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iomd_writeb(0xa0, IOMD_DMATCR);
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dma[DMA_0].dma_base = IOMD_IO0CURA;
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dma[DMA_0].dma_irq = IRQ_DMA0;
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dma[DMA_0].d_ops = &iomd_dma_ops;
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dma[DMA_1].dma_base = IOMD_IO1CURA;
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dma[DMA_1].dma_irq = IRQ_DMA1;
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dma[DMA_1].d_ops = &iomd_dma_ops;
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dma[DMA_2].dma_base = IOMD_IO2CURA;
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dma[DMA_2].dma_irq = IRQ_DMA2;
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dma[DMA_2].d_ops = &iomd_dma_ops;
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dma[DMA_3].dma_base = IOMD_IO3CURA;
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dma[DMA_3].dma_irq = IRQ_DMA3;
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dma[DMA_3].d_ops = &iomd_dma_ops;
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dma[DMA_S0].dma_base = IOMD_SD0CURA;
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dma[DMA_S0].dma_irq = IRQ_DMAS0;
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dma[DMA_S0].d_ops = &iomd_dma_ops;
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dma[DMA_S1].dma_base = IOMD_SD1CURA;
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dma[DMA_S1].dma_irq = IRQ_DMAS1;
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dma[DMA_S1].d_ops = &iomd_dma_ops;
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dma[DMA_VIRTUAL_FLOPPY].dma_irq = FIQ_FLOPPYDATA;
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dma[DMA_VIRTUAL_FLOPPY].d_ops = &floppy_dma_ops;
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dma[DMA_VIRTUAL_SOUND].d_ops = &sound_dma_ops;
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/*
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* Setup DMA channels 2,3 to be for podules
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* and channels 0,1 for internal devices
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*/
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iomd_writeb(DMA_EXT_IO3|DMA_EXT_IO2, IOMD_DMAEXT);
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}
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