657ebfadc1
clock34xx_data.c now contains data for the OMAP34xx family, the OMAP36xx family, and the OMAP3517 family, so rename it to clock3xxx_data.c. Rename clock34xx.c to clock3xxx.c, and move the chip family-specific clock functions to clock34xx.c, clock36xx.c, or clock3517.c, as appropriate. So now "clock3xxx.*" refers to the OMAP3 superset. The main goal here is to prepare to compile chip family-specific clock functions only for kernel builds that target that chip family. To get to that point, we also need to add CONFIG_SOC_* options for those other chip families; that will be done in future patches, planned for 2.6.35. OMAP4 is also affected by this. It duplicated the OMAP3 non-CORE DPLL clkops structure. The OMAP4 variant of this clkops structure has been removed, and since there was nothing else currently in clock44xx.c, it too has been removed -- it can always be added back later when there is some content for it. (The OMAP4 clock autogeneration scripts have been updated accordingly.) Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Benoît Cousson <b-cousson@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Ranjith Lohithakshan <ranjithl@ti.com> Cc: Tony Lindgren <tony@atomide.com>
73 lines
2.0 KiB
C
73 lines
2.0 KiB
C
/*
|
|
* OMAP36xx-specific clkops
|
|
*
|
|
* Copyright (C) 2010 Texas Instruments, Inc.
|
|
* Copyright (C) 2010 Nokia Corporation
|
|
*
|
|
* Mike Turquette
|
|
* Vijaykumar GN
|
|
* Paul Walmsley
|
|
*
|
|
* Parts of this code are based on code written by
|
|
* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
|
|
* Russell King
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#undef DEBUG
|
|
|
|
#include <linux/kernel.h>
|
|
#include <linux/clk.h>
|
|
#include <linux/io.h>
|
|
|
|
#include <plat/clock.h>
|
|
|
|
#include "clock.h"
|
|
#include "clock36xx.h"
|
|
|
|
|
|
/**
|
|
* omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
|
|
* from HSDivider PWRDN problem Implements Errata ID: i556.
|
|
* @clk: DPLL output struct clk
|
|
*
|
|
* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
|
|
* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
|
|
* valueafter their respective PWRDN bits are set. Any dummy write
|
|
* (Any other value different from the Read value) to the
|
|
* corresponding CM_CLKSEL register will refresh the dividers.
|
|
*/
|
|
static int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk *clk)
|
|
{
|
|
u32 dummy_v, orig_v, clksel_shift;
|
|
int ret;
|
|
|
|
/* Clear PWRDN bit of HSDIVIDER */
|
|
ret = omap2_dflt_clk_enable(clk);
|
|
|
|
/* Restore the dividers */
|
|
if (!ret) {
|
|
clksel_shift = __ffs(clk->parent->clksel_mask);
|
|
orig_v = __raw_readl(clk->parent->clksel_reg);
|
|
dummy_v = orig_v;
|
|
|
|
/* Write any other value different from the Read value */
|
|
dummy_v ^= (1 << clksel_shift);
|
|
__raw_writel(dummy_v, clk->parent->clksel_reg);
|
|
|
|
/* Write the original divider */
|
|
__raw_writel(orig_v, clk->parent->clksel_reg);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
const struct clkops clkops_omap36xx_pwrdn_with_hsdiv_wait_restore = {
|
|
.enable = omap36xx_pwrdn_clk_enable_with_hsdiv_restore,
|
|
.disable = omap2_dflt_clk_disable,
|
|
.find_companion = omap2_clk_dflt_find_companion,
|
|
.find_idlest = omap2_clk_dflt_find_idlest,
|
|
};
|