e2f04e1894
Patch from Matt Reimer There is a subtle bug in the GPIO interrupt status register handling in arch/arm/mach-imx/irq.c:imx_gpio_ack_irq(). The documentation states that a 1 should be written to the relevant bit to acknowledge a GPIO interrupt, but that is not what the code does. The problem is that the |= writes back 1s for all the *other* interrupts represented in the register, so interrupts could get lost. For example, if interrupts are pending for GPIO B10 and B12, ISR_B would have the value 0x00001400. Then when the interrupt code handles GPIO B10, it eventually calls imx_gpio_ack_irq(IRQ_GPIOB(10)), which effectively does this: ISR_B |= 1 << 10; with the result that (0x00001400 | 0x00000400) is written, clearing the interrupt status bits for *both* GPIO B10 and B12. The fix is to write 1s only for the interrupts we want to clear. The same problem seems to be occurring in the DMA code; this patch does not address those issues. Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Matt Reimer <mreimer@vpop.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
253 lines
6.0 KiB
C
253 lines
6.0 KiB
C
/*
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* linux/arch/arm/mach-imx/irq.c
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*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* 03/03/2004 Sascha Hauer <sascha@saschahauer.de>
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* Copied from the motorola bsp package and added gpio demux
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* interrupt handler
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*/
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <asm/hardware.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/mach/irq.h>
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/*
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*
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* We simply use the ENABLE DISABLE registers inside of the IMX
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* to turn on/off specific interrupts. FIXME- We should
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* also add support for the accelerated interrupt controller
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* by putting offets to irq jump code in the appropriate
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* places.
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*
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*/
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#define INTENNUM_OFF 0x8
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#define INTDISNUM_OFF 0xC
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#define VA_AITC_BASE IO_ADDRESS(IMX_AITC_BASE)
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#define IMX_AITC_INTDISNUM (VA_AITC_BASE + INTDISNUM_OFF)
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#define IMX_AITC_INTENNUM (VA_AITC_BASE + INTENNUM_OFF)
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#if 0
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#define DEBUG_IRQ(fmt...) printk(fmt)
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#else
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#define DEBUG_IRQ(fmt...) do { } while (0)
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#endif
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static void
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imx_mask_irq(unsigned int irq)
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{
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__raw_writel(irq, IMX_AITC_INTDISNUM);
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}
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static void
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imx_unmask_irq(unsigned int irq)
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{
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__raw_writel(irq, IMX_AITC_INTENNUM);
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}
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static int
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imx_gpio_irq_type(unsigned int _irq, unsigned int type)
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{
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unsigned int irq_type = 0, irq, reg, bit;
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irq = _irq - IRQ_GPIOA(0);
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reg = irq >> 5;
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bit = 1 << (irq % 32);
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if (type == IRQT_PROBE) {
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/* Don't mess with enabled GPIOs using preconfigured edges or
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GPIOs set to alternate function during probe */
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/* TODO: support probe */
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// if ((GPIO_IRQ_rising_edge[idx] | GPIO_IRQ_falling_edge[idx]) &
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// GPIO_bit(gpio))
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// return 0;
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// if (GAFR(gpio) & (0x3 << (((gpio) & 0xf)*2)))
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// return 0;
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// type = __IRQT_RISEDGE | __IRQT_FALEDGE;
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}
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GIUS(reg) |= bit;
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DDIR(reg) &= ~(bit);
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DEBUG_IRQ("setting type of irq %d to ", _irq);
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if (type & __IRQT_RISEDGE) {
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DEBUG_IRQ("rising edges\n");
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irq_type = 0x0;
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}
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if (type & __IRQT_FALEDGE) {
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DEBUG_IRQ("falling edges\n");
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irq_type = 0x1;
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}
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if (type & __IRQT_LOWLVL) {
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DEBUG_IRQ("low level\n");
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irq_type = 0x3;
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}
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if (type & __IRQT_HIGHLVL) {
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DEBUG_IRQ("high level\n");
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irq_type = 0x2;
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}
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if (irq % 32 < 16) {
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ICR1(reg) = (ICR1(reg) & ~(0x3 << ((irq % 16) * 2))) |
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(irq_type << ((irq % 16) * 2));
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} else {
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ICR2(reg) = (ICR2(reg) & ~(0x3 << ((irq % 16) * 2))) |
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(irq_type << ((irq % 16) * 2));
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}
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return 0;
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}
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static void
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imx_gpio_ack_irq(unsigned int irq)
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{
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DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
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ISR(IRQ_TO_REG(irq)) = 1 << ((irq - IRQ_GPIOA(0)) % 32);
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}
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static void
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imx_gpio_mask_irq(unsigned int irq)
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{
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DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
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IMR(IRQ_TO_REG(irq)) &= ~( 1 << ((irq - IRQ_GPIOA(0)) % 32));
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}
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static void
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imx_gpio_unmask_irq(unsigned int irq)
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{
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DEBUG_IRQ("%s: irq %d\n", __FUNCTION__, irq);
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IMR(IRQ_TO_REG(irq)) |= 1 << ((irq - IRQ_GPIOA(0)) % 32);
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}
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static void
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imx_gpio_handler(unsigned int mask, unsigned int irq,
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struct irqdesc *desc, struct pt_regs *regs)
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{
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desc = irq_desc + irq;
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while (mask) {
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if (mask & 1) {
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DEBUG_IRQ("handling irq %d\n", irq);
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desc_handle_irq(irq, desc, regs);
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}
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irq++;
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desc++;
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mask >>= 1;
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}
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}
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static void
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imx_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned int mask, irq;
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mask = ISR(0);
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irq = IRQ_GPIOA(0);
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imx_gpio_handler(mask, irq, desc, regs);
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}
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static void
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imx_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned int mask, irq;
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mask = ISR(1);
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irq = IRQ_GPIOB(0);
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imx_gpio_handler(mask, irq, desc, regs);
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}
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static void
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imx_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned int mask, irq;
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mask = ISR(2);
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irq = IRQ_GPIOC(0);
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imx_gpio_handler(mask, irq, desc, regs);
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}
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static void
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imx_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned int mask, irq;
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mask = ISR(3);
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irq = IRQ_GPIOD(0);
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imx_gpio_handler(mask, irq, desc, regs);
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}
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static struct irqchip imx_internal_chip = {
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.ack = imx_mask_irq,
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.mask = imx_mask_irq,
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.unmask = imx_unmask_irq,
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};
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static struct irqchip imx_gpio_chip = {
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.ack = imx_gpio_ack_irq,
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.mask = imx_gpio_mask_irq,
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.unmask = imx_gpio_unmask_irq,
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.set_type = imx_gpio_irq_type,
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};
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void __init
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imx_init_irq(void)
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{
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unsigned int irq;
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DEBUG_IRQ("Initializing imx interrupts\n");
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/* Mask all interrupts initially */
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IMR(0) = 0;
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IMR(1) = 0;
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IMR(2) = 0;
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IMR(3) = 0;
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for (irq = 0; irq < IMX_IRQS; irq++) {
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set_irq_chip(irq, &imx_internal_chip);
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set_irq_handler(irq, do_level_IRQ);
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set_irq_flags(irq, IRQF_VALID);
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}
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for (irq = IRQ_GPIOA(0); irq < IRQ_GPIOD(32); irq++) {
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set_irq_chip(irq, &imx_gpio_chip);
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set_irq_handler(irq, do_edge_IRQ);
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set_irq_flags(irq, IRQF_VALID);
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}
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set_irq_chained_handler(GPIO_INT_PORTA, imx_gpioa_demux_handler);
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set_irq_chained_handler(GPIO_INT_PORTB, imx_gpiob_demux_handler);
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set_irq_chained_handler(GPIO_INT_PORTC, imx_gpioc_demux_handler);
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set_irq_chained_handler(GPIO_INT_PORTD, imx_gpiod_demux_handler);
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/* Disable all interrupts initially. */
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/* In IMX this is done in the bootloader. */
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}
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