4da808c352
Some of the trap code was still assuming that alternate global %g6 was hard coded with current_thread_info(). Let's just consistently flush at KERNBASE when we need a pipeline synchronization. That's locked into the TLB and will always work. Signed-off-by: David S. Miller <davem@davemloft.net>
382 lines
11 KiB
ArmAsm
382 lines
11 KiB
ArmAsm
/* $Id: winfixup.S,v 1.30 2002/02/09 19:49:30 davem Exp $
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*
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* winfixup.S: Handle cases where user stack pointer is found to be bogus.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#include <asm/asi.h>
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#include <asm/head.h>
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#include <asm/page.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/spitfire.h>
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#include <asm/thread_info.h>
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.text
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set_pcontext:
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sethi %hi(sparc64_kern_pri_context), %l1
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ldx [%l1 + %lo(sparc64_kern_pri_context)], %l1
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mov PRIMARY_CONTEXT, %g1
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stxa %l1, [%g1] ASI_DMMU
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sethi %hi(KERNBASE), %l1
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flush %l1
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retl
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nop
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.align 32
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/* Here are the rules, pay attention.
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*
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* The kernel is disallowed from touching user space while
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* the trap level is greater than zero, except for from within
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* the window spill/fill handlers. This must be followed
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* so that we can easily detect the case where we tried to
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* spill/fill with a bogus (or unmapped) user stack pointer.
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*
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* These are layed out in a special way for cache reasons,
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* don't touch...
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*/
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.globl fill_fixup, spill_fixup
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fill_fixup:
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TRAP_LOAD_THREAD_REG
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rdpr %tstate, %g1
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andcc %g1, TSTATE_PRIV, %g0
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or %g4, FAULT_CODE_WINFIXUP, %g4
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be,pt %xcc, window_scheisse_from_user_common
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and %g1, TSTATE_CWP, %g1
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/* This is the extremely complex case, but it does happen from
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* time to time if things are just right. Essentially the restore
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* done in rtrap right before going back to user mode, with tl=1
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* and that levels trap stack registers all setup, took a fill trap,
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* the user stack was not mapped in the tlb, and tlb miss occurred,
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* the pte found was not valid, and a simple ref bit watch update
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* could not satisfy the miss, so we got here.
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*
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* We must carefully unwind the state so we get back to tl=0, preserve
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* all the register values we were going to give to the user. Luckily
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* most things are where they need to be, we also have the address
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* which triggered the fault handy as well.
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*
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* Also note that we must preserve %l5 and %l6. If the user was
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* returning from a system call, we must make it look this way
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* after we process the fill fault on the users stack.
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*
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* First, get into the window where the original restore was executed.
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*/
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rdpr %wstate, %g2 ! Grab user mode wstate.
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wrpr %g1, %cwp ! Get into the right window.
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sll %g2, 3, %g2 ! NORMAL-->OTHER
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wrpr %g0, 0x0, %canrestore ! Standard etrap stuff.
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wrpr %g2, 0x0, %wstate ! This must be consistent.
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wrpr %g0, 0x0, %otherwin ! We know this.
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call set_pcontext ! Change contexts...
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nop
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rdpr %pstate, %l1 ! Prepare to change globals.
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mov %g6, %o7 ! Get current.
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andn %l1, PSTATE_MM, %l1 ! We want to be in RMO
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stb %g4, [%g6 + TI_FAULT_CODE]
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stx %g5, [%g6 + TI_FAULT_ADDR]
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wrpr %g0, 0x0, %tl ! Out of trap levels.
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wrpr %l1, (PSTATE_IE | PSTATE_AG | PSTATE_RMO), %pstate
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mov %o7, %g6
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ldx [%g6 + TI_TASK], %g4
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LOAD_PER_CPU_BASE(%g1, %g2)
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/* This is the same as below, except we handle this a bit special
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* since we must preserve %l5 and %l6, see comment above.
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*/
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call do_sparc64_fault
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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nop ! yes, nop is correct
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/* Be very careful about usage of the alternate globals here.
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* You cannot touch %g4/%g5 as that has the fault information
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* should this be from usermode. Also be careful for the case
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* where we get here from the save instruction in etrap.S when
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* coming from either user or kernel (does not matter which, it
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* is the same problem in both cases). Essentially this means
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* do not touch %g7 or %g2 so we handle the two cases fine.
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*/
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spill_fixup:
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TRAP_LOAD_THREAD_REG
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ldx [%g6 + TI_FLAGS], %g1
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andcc %g1, _TIF_32BIT, %g0
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ldub [%g6 + TI_WSAVED], %g1
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sll %g1, 3, %g3
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add %g6, %g3, %g3
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stx %sp, [%g3 + TI_RWIN_SPTRS]
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sll %g1, 7, %g3
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bne,pt %xcc, 1f
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add %g6, %g3, %g3
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stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
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stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
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stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
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stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
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stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
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stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
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stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
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stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
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stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
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stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
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stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
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stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
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stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
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stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
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stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
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b,pt %xcc, 2f
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stx %i7, [%g3 + TI_REG_WINDOW + 0x78]
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1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
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stw %l1, [%g3 + TI_REG_WINDOW + 0x04]
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stw %l2, [%g3 + TI_REG_WINDOW + 0x08]
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stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
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stw %l4, [%g3 + TI_REG_WINDOW + 0x10]
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stw %l5, [%g3 + TI_REG_WINDOW + 0x14]
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stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
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stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]
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stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
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stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
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stw %i2, [%g3 + TI_REG_WINDOW + 0x28]
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stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]
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stw %i4, [%g3 + TI_REG_WINDOW + 0x30]
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stw %i5, [%g3 + TI_REG_WINDOW + 0x34]
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stw %i6, [%g3 + TI_REG_WINDOW + 0x38]
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stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]
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2: add %g1, 1, %g1
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stb %g1, [%g6 + TI_WSAVED]
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rdpr %tstate, %g1
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andcc %g1, TSTATE_PRIV, %g0
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saved
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and %g1, TSTATE_CWP, %g1
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be,pn %xcc, window_scheisse_from_user_common
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mov FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4
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retry
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window_scheisse_from_user_common:
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stb %g4, [%g6 + TI_FAULT_CODE]
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stx %g5, [%g6 + TI_FAULT_ADDR]
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wrpr %g1, %cwp
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ba,pt %xcc, etrap
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rd %pc, %g7
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call do_sparc64_fault
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add %sp, PTREGS_OFF, %o0
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ba,a,pt %xcc, rtrap_clr_l6
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.globl winfix_mna, fill_fixup_mna, spill_fixup_mna
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winfix_mna:
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andn %g3, 0x7f, %g3
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add %g3, 0x78, %g3
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wrpr %g3, %tnpc
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done
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fill_fixup_mna:
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TRAP_LOAD_THREAD_REG
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rdpr %tstate, %g1
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andcc %g1, TSTATE_PRIV, %g0
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be,pt %xcc, window_mna_from_user_common
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and %g1, TSTATE_CWP, %g1
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/* Please, see fill_fixup commentary about why we must preserve
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* %l5 and %l6 to preserve absolute correct semantics.
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*/
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rdpr %wstate, %g2 ! Grab user mode wstate.
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wrpr %g1, %cwp ! Get into the right window.
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sll %g2, 3, %g2 ! NORMAL-->OTHER
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wrpr %g0, 0x0, %canrestore ! Standard etrap stuff.
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wrpr %g2, 0x0, %wstate ! This must be consistent.
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wrpr %g0, 0x0, %otherwin ! We know this.
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call set_pcontext ! Change contexts...
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nop
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rdpr %pstate, %l1 ! Prepare to change globals.
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mov %g4, %o2 ! Setup args for
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mov %g5, %o1 ! final call to mem_address_unaligned.
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andn %l1, PSTATE_MM, %l1 ! We want to be in RMO
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mov %g6, %o7 ! Stash away current.
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wrpr %g0, 0x0, %tl ! Out of trap levels.
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wrpr %l1, (PSTATE_IE | PSTATE_AG | PSTATE_RMO), %pstate
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mov %o7, %g6 ! Get current back.
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ldx [%g6 + TI_TASK], %g4 ! Finish it.
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LOAD_PER_CPU_BASE(%g1, %g2)
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call mem_address_unaligned
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add %sp, PTREGS_OFF, %o0
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b,pt %xcc, rtrap
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nop ! yes, the nop is correct
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spill_fixup_mna:
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TRAP_LOAD_THREAD_REG
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ldx [%g6 + TI_FLAGS], %g1
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andcc %g1, _TIF_32BIT, %g0
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ldub [%g6 + TI_WSAVED], %g1
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sll %g1, 3, %g3
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add %g6, %g3, %g3
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stx %sp, [%g3 + TI_RWIN_SPTRS]
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sll %g1, 7, %g3
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bne,pt %xcc, 1f
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add %g6, %g3, %g3
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stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
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stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
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stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
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stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
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stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
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stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
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stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
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stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
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stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
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stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
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stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
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stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
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stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
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stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
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stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
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stx %i7, [%g3 + TI_REG_WINDOW + 0x78]
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b,pt %xcc, 2f
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add %g1, 1, %g1
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1: std %l0, [%g3 + TI_REG_WINDOW + 0x00]
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std %l2, [%g3 + TI_REG_WINDOW + 0x08]
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std %l4, [%g3 + TI_REG_WINDOW + 0x10]
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std %l6, [%g3 + TI_REG_WINDOW + 0x18]
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std %i0, [%g3 + TI_REG_WINDOW + 0x20]
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std %i2, [%g3 + TI_REG_WINDOW + 0x28]
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std %i4, [%g3 + TI_REG_WINDOW + 0x30]
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std %i6, [%g3 + TI_REG_WINDOW + 0x38]
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add %g1, 1, %g1
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2: stb %g1, [%g6 + TI_WSAVED]
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rdpr %tstate, %g1
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andcc %g1, TSTATE_PRIV, %g0
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saved
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be,pn %xcc, window_mna_from_user_common
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and %g1, TSTATE_CWP, %g1
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retry
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window_mna_from_user_common:
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wrpr %g1, %cwp
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sethi %hi(109f), %g7
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ba,pt %xcc, etrap
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109: or %g7, %lo(109b), %g7
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mov %l4, %o2
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mov %l5, %o1
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call mem_address_unaligned
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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clr %l6
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.globl winfix_dax, fill_fixup_dax, spill_fixup_dax
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winfix_dax:
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andn %g3, 0x7f, %g3
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add %g3, 0x74, %g3
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wrpr %g3, %tnpc
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done
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fill_fixup_dax:
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TRAP_LOAD_THREAD_REG
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rdpr %tstate, %g1
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andcc %g1, TSTATE_PRIV, %g0
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be,pt %xcc, window_dax_from_user_common
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and %g1, TSTATE_CWP, %g1
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/* Please, see fill_fixup commentary about why we must preserve
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* %l5 and %l6 to preserve absolute correct semantics.
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*/
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rdpr %wstate, %g2 ! Grab user mode wstate.
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wrpr %g1, %cwp ! Get into the right window.
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sll %g2, 3, %g2 ! NORMAL-->OTHER
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wrpr %g0, 0x0, %canrestore ! Standard etrap stuff.
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wrpr %g2, 0x0, %wstate ! This must be consistent.
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wrpr %g0, 0x0, %otherwin ! We know this.
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call set_pcontext ! Change contexts...
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nop
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rdpr %pstate, %l1 ! Prepare to change globals.
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mov %g4, %o1 ! Setup args for
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mov %g5, %o2 ! final call to spitfire_data_access_exception.
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andn %l1, PSTATE_MM, %l1 ! We want to be in RMO
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mov %g6, %o7 ! Stash away current.
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wrpr %g0, 0x0, %tl ! Out of trap levels.
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wrpr %l1, (PSTATE_IE | PSTATE_AG | PSTATE_RMO), %pstate
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mov %o7, %g6 ! Get current back.
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ldx [%g6 + TI_TASK], %g4 ! Finish it.
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LOAD_PER_CPU_BASE(%g1, %g2)
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call spitfire_data_access_exception
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add %sp, PTREGS_OFF, %o0
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b,pt %xcc, rtrap
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nop ! yes, the nop is correct
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spill_fixup_dax:
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TRAP_LOAD_THREAD_REG
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ldx [%g6 + TI_FLAGS], %g1
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andcc %g1, _TIF_32BIT, %g0
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ldub [%g6 + TI_WSAVED], %g1
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sll %g1, 3, %g3
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add %g6, %g3, %g3
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stx %sp, [%g3 + TI_RWIN_SPTRS]
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sll %g1, 7, %g3
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bne,pt %xcc, 1f
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add %g6, %g3, %g3
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stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
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stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
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stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
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stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
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stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
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stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
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stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
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stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
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stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
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stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
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stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
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stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
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stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
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stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
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stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
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stx %i7, [%g3 + TI_REG_WINDOW + 0x78]
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b,pt %xcc, 2f
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add %g1, 1, %g1
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1: std %l0, [%g3 + TI_REG_WINDOW + 0x00]
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std %l2, [%g3 + TI_REG_WINDOW + 0x08]
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std %l4, [%g3 + TI_REG_WINDOW + 0x10]
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std %l6, [%g3 + TI_REG_WINDOW + 0x18]
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std %i0, [%g3 + TI_REG_WINDOW + 0x20]
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std %i2, [%g3 + TI_REG_WINDOW + 0x28]
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std %i4, [%g3 + TI_REG_WINDOW + 0x30]
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std %i6, [%g3 + TI_REG_WINDOW + 0x38]
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add %g1, 1, %g1
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2: stb %g1, [%g6 + TI_WSAVED]
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rdpr %tstate, %g1
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andcc %g1, TSTATE_PRIV, %g0
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saved
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be,pn %xcc, window_dax_from_user_common
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and %g1, TSTATE_CWP, %g1
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retry
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window_dax_from_user_common:
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wrpr %g1, %cwp
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sethi %hi(109f), %g7
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ba,pt %xcc, etrap
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109: or %g7, %lo(109b), %g7
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mov %l4, %o1
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mov %l5, %o2
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call spitfire_data_access_exception
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add %sp, PTREGS_OFF, %o0
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ba,pt %xcc, rtrap
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clr %l6
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