a8f67f4b4d
This adds support for the SH7263 (SH-2A) CPU. This particular CPU is a superset of SH7203, adding some additional peripheral blocks and hooking up additional (reserved on SH7203) vectors in the INTC block. No visibly nasty surprises, yet.. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
320 lines
11 KiB
C
320 lines
11 KiB
C
/*
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* SH7203 and SH7263 Setup
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*
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* Copyright (C) 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <asm/sci.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
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PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
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DMAC0_DEI, DMAC0_HEI, DMAC1_DEI, DMAC1_HEI,
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DMAC2_DEI, DMAC2_HEI, DMAC3_DEI, DMAC3_HEI,
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DMAC4_DEI, DMAC4_HEI, DMAC5_DEI, DMAC5_HEI,
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DMAC6_DEI, DMAC6_HEI, DMAC7_DEI, DMAC7_HEI,
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USB, LCDC, CMT0, CMT1, BSC, WDT,
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MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D,
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MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F,
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MTU2_TGI1A, MTU2_TGI1B, MTU2_TCI1V, MTU2_TCI1U,
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MTU2_TGI2A, MTU2_TGI2B, MTU2_TCI2V, MTU2_TCI2U,
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MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D, MTU2_TCI3V,
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MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D, MTU2_TCI4V,
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ADC_ADI,
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IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI, IIC30_TEI,
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IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI, IIC31_TEI,
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IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI, IIC32_TEI,
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IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI, IIC33_TEI,
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SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
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SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
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SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
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SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
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SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI,
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SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI,
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SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
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/* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
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ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG, ROMDEC_ISEC, ROMDEC_IBUF,
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ROMDEC_IREADY,
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FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
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SDHI3, SDHI0, SDHI1,
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RTC_ARM, RTC_PRD, RTC_CUP,
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RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1, RCAN0_SLE,
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RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1, RCAN1_SLE,
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SRC_OVF, SRC_ODFI, SRC_IDEI, IEBI,
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/* interrupt groups */
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PINT, DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
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MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
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MTU3_ABCD, MTU4_ABCD,
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IIC30, IIC31, IIC32, IIC33, SCIF0, SCIF1, SCIF2, SCIF3,
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SSU0, SSU1, ROMDEC, SDHI, FLCTL, RTC, RCAN0, RCAN1, SRC
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
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INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
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INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
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INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
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INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
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INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
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INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
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INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
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INTC_IRQ(DMAC0_DEI, 108), INTC_IRQ(DMAC0_HEI, 109),
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INTC_IRQ(DMAC1_DEI, 112), INTC_IRQ(DMAC1_HEI, 113),
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INTC_IRQ(DMAC2_DEI, 116), INTC_IRQ(DMAC2_HEI, 117),
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INTC_IRQ(DMAC3_DEI, 120), INTC_IRQ(DMAC3_HEI, 121),
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INTC_IRQ(DMAC4_DEI, 124), INTC_IRQ(DMAC4_HEI, 125),
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INTC_IRQ(DMAC5_DEI, 128), INTC_IRQ(DMAC5_HEI, 129),
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INTC_IRQ(DMAC6_DEI, 132), INTC_IRQ(DMAC6_HEI, 133),
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INTC_IRQ(DMAC7_DEI, 136), INTC_IRQ(DMAC7_HEI, 137),
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INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
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INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
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INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
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INTC_IRQ(MTU2_TGI0A, 146), INTC_IRQ(MTU2_TGI0B, 147),
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INTC_IRQ(MTU2_TGI0C, 148), INTC_IRQ(MTU2_TGI0D, 149),
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INTC_IRQ(MTU2_TCI0V, 150),
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INTC_IRQ(MTU2_TGI0E, 151), INTC_IRQ(MTU2_TGI0F, 152),
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INTC_IRQ(MTU2_TGI1A, 153), INTC_IRQ(MTU2_TGI1B, 154),
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INTC_IRQ(MTU2_TCI1V, 155), INTC_IRQ(MTU2_TCI1U, 156),
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INTC_IRQ(MTU2_TGI2A, 157), INTC_IRQ(MTU2_TGI2B, 158),
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INTC_IRQ(MTU2_TCI2V, 159), INTC_IRQ(MTU2_TCI2U, 160),
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INTC_IRQ(MTU2_TGI3A, 161), INTC_IRQ(MTU2_TGI3B, 162),
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INTC_IRQ(MTU2_TGI3C, 163), INTC_IRQ(MTU2_TGI3D, 164),
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INTC_IRQ(MTU2_TCI3V, 165),
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INTC_IRQ(MTU2_TGI4A, 166), INTC_IRQ(MTU2_TGI4B, 167),
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INTC_IRQ(MTU2_TGI4C, 168), INTC_IRQ(MTU2_TGI4D, 169),
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INTC_IRQ(MTU2_TCI4V, 170),
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INTC_IRQ(ADC_ADI, 171),
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INTC_IRQ(IIC30_STPI, 172), INTC_IRQ(IIC30_NAKI, 173),
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INTC_IRQ(IIC30_RXI, 174), INTC_IRQ(IIC30_TXI, 175),
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INTC_IRQ(IIC30_TEI, 176),
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INTC_IRQ(IIC31_STPI, 177), INTC_IRQ(IIC31_NAKI, 178),
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INTC_IRQ(IIC31_RXI, 179), INTC_IRQ(IIC31_TXI, 180),
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INTC_IRQ(IIC31_TEI, 181),
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INTC_IRQ(IIC32_STPI, 182), INTC_IRQ(IIC32_NAKI, 183),
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INTC_IRQ(IIC32_RXI, 184), INTC_IRQ(IIC32_TXI, 185),
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INTC_IRQ(IIC32_TEI, 186),
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INTC_IRQ(IIC33_STPI, 187), INTC_IRQ(IIC33_NAKI, 188),
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INTC_IRQ(IIC33_RXI, 189), INTC_IRQ(IIC33_TXI, 190),
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INTC_IRQ(IIC33_TEI, 191),
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INTC_IRQ(SCIF0_BRI, 192), INTC_IRQ(SCIF0_ERI, 193),
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INTC_IRQ(SCIF0_RXI, 194), INTC_IRQ(SCIF0_TXI, 195),
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INTC_IRQ(SCIF1_BRI, 196), INTC_IRQ(SCIF1_ERI, 197),
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INTC_IRQ(SCIF1_RXI, 198), INTC_IRQ(SCIF1_TXI, 199),
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INTC_IRQ(SCIF2_BRI, 200), INTC_IRQ(SCIF2_ERI, 201),
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INTC_IRQ(SCIF2_RXI, 202), INTC_IRQ(SCIF2_TXI, 203),
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INTC_IRQ(SCIF3_BRI, 204), INTC_IRQ(SCIF3_ERI, 205),
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INTC_IRQ(SCIF3_RXI, 206), INTC_IRQ(SCIF3_TXI, 207),
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INTC_IRQ(SSU0_SSERI, 208), INTC_IRQ(SSU0_SSRXI, 209),
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INTC_IRQ(SSU0_SSTXI, 210),
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INTC_IRQ(SSU1_SSERI, 211), INTC_IRQ(SSU1_SSRXI, 212),
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INTC_IRQ(SSU1_SSTXI, 213),
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INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
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INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
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INTC_IRQ(FLCTL_FLSTEI, 224), INTC_IRQ(FLCTL_FLTENDI, 225),
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INTC_IRQ(FLCTL_FLTREQ0I, 226), INTC_IRQ(FLCTL_FLTREQ1I, 227),
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INTC_IRQ(RTC_ARM, 231), INTC_IRQ(RTC_PRD, 232),
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INTC_IRQ(RTC_CUP, 233),
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INTC_IRQ(RCAN0_ERS, 234), INTC_IRQ(RCAN0_OVR, 235),
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INTC_IRQ(RCAN0_RM0, 236), INTC_IRQ(RCAN0_RM1, 237),
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INTC_IRQ(RCAN0_SLE, 238),
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INTC_IRQ(RCAN1_ERS, 239), INTC_IRQ(RCAN1_OVR, 240),
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INTC_IRQ(RCAN1_RM0, 241), INTC_IRQ(RCAN1_RM1, 242),
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INTC_IRQ(RCAN1_SLE, 243),
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/* SH7263-specific trash */
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#ifdef CONFIG_CPU_SUBTYPE_SH7263
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INTC_IRQ(ROMDEC_ISY, 218), INTC_IRQ(ROMDEC_IERR, 219),
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INTC_IRQ(ROMDEC_IARG, 220), INTC_IRQ(ROMDEC_ISEC, 221),
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INTC_IRQ(ROMDEC_IBUF, 222), INTC_IRQ(ROMDEC_IREADY, 223),
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INTC_IRQ(SDHI3, 228), INTC_IRQ(SDHI0, 229), INTC_IRQ(SDHI1, 230),
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INTC_IRQ(SRC_OVF, 244), INTC_IRQ(SRC_ODFI, 245),
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INTC_IRQ(SRC_IDEI, 246),
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INTC_IRQ(IEBI, 247),
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#endif
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};
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static struct intc_group groups[] __initdata = {
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INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
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PINT4, PINT5, PINT6, PINT7),
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INTC_GROUP(DMAC0, DMAC0_DEI, DMAC0_HEI),
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INTC_GROUP(DMAC1, DMAC1_DEI, DMAC1_HEI),
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INTC_GROUP(DMAC2, DMAC2_DEI, DMAC2_HEI),
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INTC_GROUP(DMAC3, DMAC3_DEI, DMAC3_HEI),
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INTC_GROUP(DMAC4, DMAC4_DEI, DMAC4_HEI),
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INTC_GROUP(DMAC5, DMAC5_DEI, DMAC5_HEI),
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INTC_GROUP(DMAC6, DMAC6_DEI, DMAC6_HEI),
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INTC_GROUP(DMAC7, DMAC7_DEI, DMAC7_HEI),
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INTC_GROUP(MTU0_ABCD, MTU2_TGI0A, MTU2_TGI0B, MTU2_TGI0C, MTU2_TGI0D),
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INTC_GROUP(MTU0_VEF, MTU2_TCI0V, MTU2_TGI0E, MTU2_TGI0F),
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INTC_GROUP(MTU1_AB, MTU2_TGI1A, MTU2_TGI1B),
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INTC_GROUP(MTU1_VU, MTU2_TCI1V, MTU2_TCI1U),
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INTC_GROUP(MTU2_AB, MTU2_TGI2A, MTU2_TGI2B),
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INTC_GROUP(MTU2_VU, MTU2_TCI2V, MTU2_TCI2U),
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INTC_GROUP(MTU3_ABCD, MTU2_TGI3A, MTU2_TGI3B, MTU2_TGI3C, MTU2_TGI3D),
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INTC_GROUP(MTU4_ABCD, MTU2_TGI4A, MTU2_TGI4B, MTU2_TGI4C, MTU2_TGI4D),
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INTC_GROUP(IIC30, IIC30_STPI, IIC30_NAKI, IIC30_RXI, IIC30_TXI,
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IIC30_TEI),
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INTC_GROUP(IIC31, IIC31_STPI, IIC31_NAKI, IIC31_RXI, IIC31_TXI,
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IIC31_TEI),
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INTC_GROUP(IIC32, IIC32_STPI, IIC32_NAKI, IIC32_RXI, IIC32_TXI,
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IIC32_TEI),
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INTC_GROUP(IIC33, IIC33_STPI, IIC33_NAKI, IIC33_RXI, IIC33_TXI,
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IIC33_TEI),
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INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
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INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
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INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
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INTC_GROUP(SSU0, SSU0_SSERI, SSU0_SSRXI, SSU0_SSTXI),
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INTC_GROUP(SSU1, SSU1_SSERI, SSU1_SSRXI, SSU1_SSTXI),
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INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I,
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FLCTL_FLTREQ1I),
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INTC_GROUP(RTC, RTC_ARM, RTC_PRD, RTC_CUP),
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INTC_GROUP(RCAN0, RCAN0_ERS, RCAN0_OVR, RCAN0_RM0, RCAN0_RM1,
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RCAN0_SLE),
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INTC_GROUP(RCAN1, RCAN1_ERS, RCAN1_OVR, RCAN1_RM0, RCAN1_RM1,
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RCAN1_SLE),
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#ifdef CONFIG_CPU_SUBTYPE_SH7263
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INTC_GROUP(ROMDEC, ROMDEC_ISY, ROMDEC_IERR, ROMDEC_IARG,
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ROMDEC_ISEC, ROMDEC_IBUF, ROMDEC_IREADY),
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INTC_GROUP(SDHI, SDHI3, SDHI0, SDHI1),
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INTC_GROUP(SRC, SRC_OVF, SRC_ODFI, SRC_IDEI),
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#endif
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
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{ 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
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{ 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
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{ 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
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{ 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
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{ 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
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{ 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
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{ 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
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MTU2_VU } },
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{ 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
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MTU2_TCI4V } },
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{ 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
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{ 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
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{ 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
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#ifdef CONFIG_CPU_SUBTYPE_SH7203
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{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
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SSI3_SSII, 0 } },
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{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
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{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
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#else
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{ 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
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SSI3_SSII, ROMDEC } },
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{ 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
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{ 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
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#endif
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfffe0808, 0, 16, /* PINTER */
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{ 0, 0, 0, 0, 0, 0, 0, 0,
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PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
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NULL, mask_registers, prio_registers, NULL);
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xfffe8000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 193, 194, 195, 192 },
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}, {
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.mapbase = 0xfffe8800,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 197, 198, 199, 196 },
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}, {
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.mapbase = 0xfffe9000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 201, 202, 203, 200 },
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}, {
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.mapbase = 0xfffe9800,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 205, 206, 207, 204 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xffff2000,
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.end = 0xffff2000 + 0x58 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Period IRQ */
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.start = 232,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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/* Carry IRQ */
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.start = 233,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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/* Alarm IRQ */
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.start = 231,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct platform_device *sh7203_devices[] __initdata = {
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&sci_device,
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&rtc_device,
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};
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static int __init sh7203_devices_setup(void)
|
|
{
|
|
return platform_add_devices(sh7203_devices,
|
|
ARRAY_SIZE(sh7203_devices));
|
|
}
|
|
__initcall(sh7203_devices_setup);
|
|
|
|
void __init plat_irq_setup(void)
|
|
{
|
|
register_intc_controller(&intc_desc);
|
|
}
|