af4ad9bca0
All 10Xpress PHYs require autonegotiation all the time; enforce this in the set_settings() method and do not treat it as a workaround. Remove claimed support for 100M HD mode since it is not supported by current firmware. Do not set speed override bits when AN is enabled, and do not use register 1.49192 for AN configuration as it can override what we set elsewhere. Always set the AN selector bits to 1 (802.3). Fix confusion between Next Page and Extended Next Page. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
312 lines
10 KiB
C
312 lines
10 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2006-2008 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#ifndef EFX_MDIO_10G_H
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#define EFX_MDIO_10G_H
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/*
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* Definitions needed for doing 10G MDIO as specified in clause 45
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* MDIO, which do not appear in Linux yet. Also some helper functions.
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*/
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#include "efx.h"
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#include "boards.h"
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/* Numbering of the MDIO Manageable Devices (MMDs) */
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/* Physical Medium Attachment/ Physical Medium Dependent sublayer */
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#define MDIO_MMD_PMAPMD (1)
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/* WAN Interface Sublayer */
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#define MDIO_MMD_WIS (2)
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/* Physical Coding Sublayer */
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#define MDIO_MMD_PCS (3)
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/* PHY Extender Sublayer */
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#define MDIO_MMD_PHYXS (4)
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/* Extender Sublayer */
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#define MDIO_MMD_DTEXS (5)
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/* Transmission convergence */
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#define MDIO_MMD_TC (6)
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/* Auto negotiation */
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#define MDIO_MMD_AN (7)
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/* Clause 22 extension */
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#define MDIO_MMD_C22EXT 29
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/* Generic register locations */
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#define MDIO_MMDREG_CTRL1 (0)
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#define MDIO_MMDREG_STAT1 (1)
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#define MDIO_MMDREG_IDHI (2)
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#define MDIO_MMDREG_IDLOW (3)
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#define MDIO_MMDREG_SPEED (4)
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#define MDIO_MMDREG_DEVS0 (5)
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#define MDIO_MMDREG_DEVS1 (6)
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#define MDIO_MMDREG_CTRL2 (7)
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#define MDIO_MMDREG_STAT2 (8)
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#define MDIO_MMDREG_TXDIS (9)
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/* Bits in MMDREG_CTRL1 */
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/* Reset */
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#define MDIO_MMDREG_CTRL1_RESET_LBN (15)
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#define MDIO_MMDREG_CTRL1_RESET_WIDTH (1)
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/* Loopback */
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/* Loopback bit for WIS, PCS, PHYSX and DTEXS */
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#define MDIO_MMDREG_CTRL1_LBACK_LBN (14)
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#define MDIO_MMDREG_CTRL1_LBACK_WIDTH (1)
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/* Low power */
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#define MDIO_MMDREG_CTRL1_LPOWER_LBN (11)
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#define MDIO_MMDREG_CTRL1_LPOWER_WIDTH (1)
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/* Bits in MMDREG_STAT1 */
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#define MDIO_MMDREG_STAT1_FAULT_LBN (7)
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#define MDIO_MMDREG_STAT1_FAULT_WIDTH (1)
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/* Link state */
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#define MDIO_MMDREG_STAT1_LINK_LBN (2)
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#define MDIO_MMDREG_STAT1_LINK_WIDTH (1)
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/* Low power ability */
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#define MDIO_MMDREG_STAT1_LPABLE_LBN (1)
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#define MDIO_MMDREG_STAT1_LPABLE_WIDTH (1)
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/* Bits in ID reg */
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#define MDIO_ID_REV(_id32) (_id32 & 0xf)
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#define MDIO_ID_MODEL(_id32) ((_id32 >> 4) & 0x3f)
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#define MDIO_ID_OUI(_id32) (_id32 >> 10)
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/* Bits in MMDREG_DEVS0/1. Someone thoughtfully layed things out
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* so the 'bit present' bit number of an MMD is the number of
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* that MMD */
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#define DEV_PRESENT_BIT(_b) (1 << _b)
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#define MDIO_MMDREG_DEVS_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS)
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#define MDIO_MMDREG_DEVS_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS)
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#define MDIO_MMDREG_DEVS_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD)
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#define MDIO_MMDREG_DEVS_AN DEV_PRESENT_BIT(MDIO_MMD_AN)
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#define MDIO_MMDREG_DEVS_C22EXT DEV_PRESENT_BIT(MDIO_MMD_C22EXT)
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/* Bits in MMDREG_SPEED */
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#define MDIO_MMDREG_SPEED_10G_LBN 0
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#define MDIO_MMDREG_SPEED_10G_WIDTH 1
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#define MDIO_MMDREG_SPEED_1000M_LBN 4
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#define MDIO_MMDREG_SPEED_1000M_WIDTH 1
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#define MDIO_MMDREG_SPEED_100M_LBN 5
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#define MDIO_MMDREG_SPEED_100M_WIDTH 1
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#define MDIO_MMDREG_SPEED_10M_LBN 6
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#define MDIO_MMDREG_SPEED_10M_WIDTH 1
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/* Bits in MMDREG_STAT2 */
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#define MDIO_MMDREG_STAT2_PRESENT_VAL (2)
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#define MDIO_MMDREG_STAT2_PRESENT_LBN (14)
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#define MDIO_MMDREG_STAT2_PRESENT_WIDTH (2)
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/* Bits in MMDREG_TXDIS */
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#define MDIO_MMDREG_TXDIS_GLOBAL_LBN (0)
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#define MDIO_MMDREG_TXDIS_GLOBAL_WIDTH (1)
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/* MMD-specific bits, ordered by MMD, then register */
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#define MDIO_PMAPMD_CTRL1_LBACK_LBN (0)
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#define MDIO_PMAPMD_CTRL1_LBACK_WIDTH (1)
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/* PMA type (4 bits) */
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#define MDIO_PMAPMD_CTRL2_10G_CX4 (0x0)
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#define MDIO_PMAPMD_CTRL2_10G_EW (0x1)
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#define MDIO_PMAPMD_CTRL2_10G_LW (0x2)
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#define MDIO_PMAPMD_CTRL2_10G_SW (0x3)
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#define MDIO_PMAPMD_CTRL2_10G_LX4 (0x4)
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#define MDIO_PMAPMD_CTRL2_10G_ER (0x5)
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#define MDIO_PMAPMD_CTRL2_10G_LR (0x6)
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#define MDIO_PMAPMD_CTRL2_10G_SR (0x7)
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/* Reserved */
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#define MDIO_PMAPMD_CTRL2_10G_BT (0x9)
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/* Reserved */
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/* Reserved */
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#define MDIO_PMAPMD_CTRL2_1G_BT (0xc)
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/* Reserved */
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#define MDIO_PMAPMD_CTRL2_100_BT (0xe)
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#define MDIO_PMAPMD_CTRL2_10_BT (0xf)
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#define MDIO_PMAPMD_CTRL2_TYPE_MASK (0xf)
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/* PMA 10GBT registers */
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#define MDIO_PMAPMD_10GBT_TXPWR (131)
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#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_LBN (0)
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#define MDIO_PMAPMD_10GBT_TXPWR_SHORT_WIDTH (1)
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/* PHY XGXS Status 2 */
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#define MDIO_PHYXS_STATUS2 (8)
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#define MDIO_PHYXS_STATUS2_RX_FAULT_LBN 10
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/* PHY XGXS lane state */
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#define MDIO_PHYXS_LANE_STATE (0x18)
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#define MDIO_PHYXS_LANE_ALIGNED_LBN (12)
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/* AN registers */
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#define MDIO_AN_CTRL_XNP_LBN 13
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#define MDIO_AN_STATUS (1)
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#define MDIO_AN_STATUS_XNP_LBN (7)
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#define MDIO_AN_STATUS_PAGE_LBN (6)
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#define MDIO_AN_STATUS_AN_DONE_LBN (5)
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#define MDIO_AN_STATUS_LP_AN_CAP_LBN (0)
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#define MDIO_AN_ADVERTISE 16
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#define MDIO_AN_ADVERTISE_XNP_LBN 12
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#define MDIO_AN_LPA 19
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#define MDIO_AN_XNP 22
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#define MDIO_AN_LPA_XNP 25
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#define MDIO_AN_10GBT_CTRL 32
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#define MDIO_AN_10GBT_CTRL_ADV_10G_LBN 12
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#define MDIO_AN_10GBT_STATUS (33)
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#define MDIO_AN_10GBT_STATUS_MS_FLT_LBN (15) /* MASTER/SLAVE config fault */
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#define MDIO_AN_10GBT_STATUS_MS_LBN (14) /* MASTER/SLAVE config */
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#define MDIO_AN_10GBT_STATUS_LOC_OK_LBN (13) /* Local OK */
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#define MDIO_AN_10GBT_STATUS_REM_OK_LBN (12) /* Remote OK */
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#define MDIO_AN_10GBT_STATUS_LP_10G_LBN (11) /* Link partner is 10GBT capable */
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#define MDIO_AN_10GBT_STATUS_LP_LTA_LBN (10) /* LP loop timing ability */
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#define MDIO_AN_10GBT_STATUS_LP_TRR_LBN (9) /* LP Training Reset Request */
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/* Packing of the prt and dev arguments of clause 45 style MDIO into a
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* single int so they can be passed into the mdio_read/write functions
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* that currently exist. Note that as Falcon is the only current user,
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* the packed form is chosen to match what Falcon needs to write into
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* a register. This is checked at compile-time so do not change it. If
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* your target chip needs things layed out differently you will need
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* to unpack the arguments in your chip-specific mdio functions.
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*/
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/* These are defined by the standard. */
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#define MDIO45_PRT_ID_WIDTH (5)
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#define MDIO45_DEV_ID_WIDTH (5)
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/* The prt ID is just packed in immediately to the left of the dev ID */
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#define MDIO45_PRT_DEV_WIDTH (MDIO45_PRT_ID_WIDTH + MDIO45_DEV_ID_WIDTH)
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#define MDIO45_PRT_ID_MASK ((1 << MDIO45_PRT_DEV_WIDTH) - 1)
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/* This is the prt + dev extended by 1 bit to hold the 'is clause 45' flag. */
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#define MDIO45_XPRT_ID_WIDTH (MDIO45_PRT_DEV_WIDTH + 1)
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#define MDIO45_XPRT_ID_MASK ((1 << MDIO45_XPRT_ID_WIDTH) - 1)
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#define MDIO45_XPRT_ID_IS10G (1 << (MDIO45_XPRT_ID_WIDTH - 1))
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#define MDIO45_PRT_ID_COMP_LBN MDIO45_DEV_ID_WIDTH
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#define MDIO45_PRT_ID_COMP_WIDTH MDIO45_PRT_ID_WIDTH
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#define MDIO45_DEV_ID_COMP_LBN 0
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#define MDIO45_DEV_ID_COMP_WIDTH MDIO45_DEV_ID_WIDTH
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/* Compose port and device into a phy_id */
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static inline int mdio_clause45_pack(u8 prt, u8 dev)
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{
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efx_dword_t phy_id;
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EFX_POPULATE_DWORD_2(phy_id, MDIO45_PRT_ID_COMP, prt,
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MDIO45_DEV_ID_COMP, dev);
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return MDIO45_XPRT_ID_IS10G | EFX_DWORD_VAL(phy_id);
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}
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static inline void mdio_clause45_unpack(u32 val, u8 *prt, u8 *dev)
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{
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efx_dword_t phy_id;
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EFX_POPULATE_DWORD_1(phy_id, EFX_DWORD_0, val);
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*prt = EFX_DWORD_FIELD(phy_id, MDIO45_PRT_ID_COMP);
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*dev = EFX_DWORD_FIELD(phy_id, MDIO45_DEV_ID_COMP);
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}
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static inline int mdio_clause45_read(struct efx_nic *efx,
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u8 prt, u8 dev, u16 addr)
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{
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return efx->mii.mdio_read(efx->net_dev,
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mdio_clause45_pack(prt, dev), addr);
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}
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static inline void mdio_clause45_write(struct efx_nic *efx,
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u8 prt, u8 dev, u16 addr, int value)
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{
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efx->mii.mdio_write(efx->net_dev,
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mdio_clause45_pack(prt, dev), addr, value);
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}
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static inline u32 mdio_clause45_read_id(struct efx_nic *efx, int mmd)
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{
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int phy_id = efx->mii.phy_id;
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u16 id_low = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_IDLOW);
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u16 id_hi = mdio_clause45_read(efx, phy_id, mmd, MDIO_MMDREG_IDHI);
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return (id_hi << 16) | (id_low);
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}
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static inline bool mdio_clause45_phyxgxs_lane_sync(struct efx_nic *efx)
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{
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int i, lane_status;
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bool sync;
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for (i = 0; i < 2; ++i)
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lane_status = mdio_clause45_read(efx, efx->mii.phy_id,
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MDIO_MMD_PHYXS,
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MDIO_PHYXS_LANE_STATE);
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sync = !!(lane_status & (1 << MDIO_PHYXS_LANE_ALIGNED_LBN));
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if (!sync)
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EFX_LOG(efx, "XGXS lane status: %x\n", lane_status);
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return sync;
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}
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extern const char *mdio_clause45_mmd_name(int mmd);
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/*
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* Reset a specific MMD and wait for reset to clear.
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* Return number of spins left (>0) on success, -%ETIMEDOUT on failure.
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*
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* This function will sleep
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*/
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extern int mdio_clause45_reset_mmd(struct efx_nic *efx, int mmd,
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int spins, int spintime);
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/* As mdio_clause45_check_mmd but for multiple MMDs */
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int mdio_clause45_check_mmds(struct efx_nic *efx,
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unsigned int mmd_mask, unsigned int fatal_mask);
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/* Check the link status of specified mmds in bit mask */
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extern bool mdio_clause45_links_ok(struct efx_nic *efx,
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unsigned int mmd_mask);
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/* Generic transmit disable support though PMAPMD */
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extern void mdio_clause45_transmit_disable(struct efx_nic *efx);
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/* Generic part of reconfigure: set/clear loopback bits */
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extern void mdio_clause45_phy_reconfigure(struct efx_nic *efx);
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/* Set the power state of the specified MMDs */
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extern void mdio_clause45_set_mmds_lpower(struct efx_nic *efx,
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int low_power, unsigned int mmd_mask);
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/* Read (some of) the PHY settings over MDIO */
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extern void mdio_clause45_get_settings(struct efx_nic *efx,
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struct ethtool_cmd *ecmd);
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/* Read (some of) the PHY settings over MDIO */
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extern void
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mdio_clause45_get_settings_ext(struct efx_nic *efx, struct ethtool_cmd *ecmd,
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u32 xnp, u32 xnp_lpa);
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/* Set (some of) the PHY settings over MDIO */
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extern int mdio_clause45_set_settings(struct efx_nic *efx,
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struct ethtool_cmd *ecmd);
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/* Set pause parameters to be advertised through AN (if available) */
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extern void mdio_clause45_set_pause(struct efx_nic *efx);
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/* Get pause parameters from AN if available (otherwise return
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* requested pause parameters)
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*/
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enum efx_fc_type mdio_clause45_get_pause(struct efx_nic *efx);
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/* Wait for specified MMDs to exit reset within a timeout */
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extern int mdio_clause45_wait_reset_mmds(struct efx_nic *efx,
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unsigned int mmd_mask);
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/* Set or clear flag, debouncing */
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extern void mdio_clause45_set_flag(struct efx_nic *efx, u8 prt, u8 dev,
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u16 addr, int bit, bool sense);
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#endif /* EFX_MDIO_10G_H */
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