d3cb487149
Several counters already have the need to use 64 atomic variables on 64 bit platforms (see mm_counter_t in sched.h). We have to do ugly ifdefs to fall back to 32 bit atomic on 32 bit platforms. The VM statistics patch that I am working on will also make more extensive use of atomic64. This patch introduces a new type atomic_long_t by providing definitions in asm-generic/atomic.h that works similar to the c "long" type. Its 32 bits on 32 bit platforms and 64 bits on 64 bit platforms. Also cleans up the determination of the mm_counter_t in sched.h. Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
718 lines
17 KiB
C
718 lines
17 KiB
C
/*
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* Atomic operations that C can't guarantee us. Useful for
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* resource counting etc..
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*
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* But use these as seldom as possible since they are much more slower
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* than regular operations.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 97, 99, 2000, 03, 04 by Ralf Baechle
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*/
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/*
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* As workaround for the ATOMIC_DEC_AND_LOCK / atomic_dec_and_lock mess in
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* <linux/spinlock.h> we have to include <linux/spinlock.h> outside the
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* main big wrapper ...
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*/
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#include <linux/config.h>
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#include <linux/spinlock.h>
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <asm/cpu-features.h>
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#include <asm/war.h>
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extern spinlock_t atomic_lock;
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typedef struct { volatile int counter; } atomic_t;
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#define ATOMIC_INIT(i) { (i) }
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/*
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* atomic_read - read atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically reads the value of @v.
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*/
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#define atomic_read(v) ((v)->counter)
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/*
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* atomic_set - set atomic variable
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* @v: pointer of type atomic_t
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* @i: required value
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*
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* Atomically sets the value of @v to @i.
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*/
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#define atomic_set(v,i) ((v)->counter = (i))
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/*
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* atomic_add - add integer to atomic variable
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* @i: integer value to add
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* @v: pointer of type atomic_t
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*
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* Atomically adds @i to @v.
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*/
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static __inline__ void atomic_add(int i, atomic_t * v)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %1 # atomic_add \n"
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" addu %0, %2 \n"
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" sc %0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter));
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} else if (cpu_has_llsc) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %1 # atomic_add \n"
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" addu %0, %2 \n"
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" sc %0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter));
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} else {
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unsigned long flags;
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spin_lock_irqsave(&atomic_lock, flags);
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v->counter += i;
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spin_unlock_irqrestore(&atomic_lock, flags);
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}
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}
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/*
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* atomic_sub - subtract the atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically subtracts @i from @v.
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*/
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static __inline__ void atomic_sub(int i, atomic_t * v)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %1 # atomic_sub \n"
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" subu %0, %2 \n"
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" sc %0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter));
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} else if (cpu_has_llsc) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %0, %1 # atomic_sub \n"
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" subu %0, %2 \n"
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" sc %0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter));
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} else {
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unsigned long flags;
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spin_lock_irqsave(&atomic_lock, flags);
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v->counter -= i;
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spin_unlock_irqrestore(&atomic_lock, flags);
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}
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}
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/*
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* Same as above, but return the result value
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*/
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static __inline__ int atomic_add_return(int i, atomic_t * v)
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{
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unsigned long result;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %1, %2 # atomic_add_return \n"
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" addu %0, %1, %3 \n"
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" sc %0, %2 \n"
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" beqzl %0, 1b \n"
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" addu %0, %1, %3 \n"
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" sync \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter)
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: "memory");
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} else if (cpu_has_llsc) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %1, %2 # atomic_add_return \n"
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" addu %0, %1, %3 \n"
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" sc %0, %2 \n"
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" beqz %0, 1b \n"
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" addu %0, %1, %3 \n"
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" sync \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter)
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: "memory");
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} else {
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unsigned long flags;
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spin_lock_irqsave(&atomic_lock, flags);
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result = v->counter;
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result += i;
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v->counter = result;
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spin_unlock_irqrestore(&atomic_lock, flags);
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}
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return result;
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}
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static __inline__ int atomic_sub_return(int i, atomic_t * v)
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{
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unsigned long result;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %1, %2 # atomic_sub_return \n"
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" subu %0, %1, %3 \n"
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" sc %0, %2 \n"
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" beqzl %0, 1b \n"
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" subu %0, %1, %3 \n"
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" sync \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter)
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: "memory");
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} else if (cpu_has_llsc) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %1, %2 # atomic_sub_return \n"
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" subu %0, %1, %3 \n"
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" sc %0, %2 \n"
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" beqz %0, 1b \n"
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" subu %0, %1, %3 \n"
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" sync \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter)
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: "memory");
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} else {
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unsigned long flags;
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spin_lock_irqsave(&atomic_lock, flags);
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result = v->counter;
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result -= i;
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v->counter = result;
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spin_unlock_irqrestore(&atomic_lock, flags);
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}
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return result;
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}
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/*
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* atomic_sub_if_positive - conditionally subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically test @v and subtract @i if @v is greater or equal than @i.
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* The function returns the old value of @v minus @i.
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*/
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static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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{
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unsigned long result;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %1, %2 # atomic_sub_if_positive\n"
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" subu %0, %1, %3 \n"
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" bltz %0, 1f \n"
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" sc %0, %2 \n"
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" beqzl %0, 1b \n"
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" sync \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter)
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: "memory");
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} else if (cpu_has_llsc) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: ll %1, %2 # atomic_sub_if_positive\n"
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" subu %0, %1, %3 \n"
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" bltz %0, 1f \n"
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" sc %0, %2 \n"
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" beqz %0, 1b \n"
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" sync \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter)
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: "memory");
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} else {
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unsigned long flags;
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spin_lock_irqsave(&atomic_lock, flags);
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result = v->counter;
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result -= i;
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if (result >= 0)
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v->counter = result;
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spin_unlock_irqrestore(&atomic_lock, flags);
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}
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return result;
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}
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#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
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/**
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* atomic_add_unless - add unless the number is a given value
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* @v: pointer of type atomic_t
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* @a: the amount to add to v...
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* @u: ...unless v is equal to u.
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*
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* Atomically adds @a to @v, so long as it was not @u.
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* Returns non-zero if @v was not @u, and zero otherwise.
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*/
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#define atomic_add_unless(v, a, u) \
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({ \
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int c, old; \
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c = atomic_read(v); \
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while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
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c = old; \
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c != (u); \
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})
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#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
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#define atomic_dec_return(v) atomic_sub_return(1,(v))
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#define atomic_inc_return(v) atomic_add_return(1,(v))
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/*
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* atomic_sub_and_test - subtract value from variable and test result
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically subtracts @i from @v and returns
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* true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
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/*
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* atomic_inc_and_test - increment and test
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1
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* and returns true if the result is zero, or false for all
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* other cases.
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*/
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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/*
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* atomic_dec_and_test - decrement by 1 and test
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* @v: pointer of type atomic_t
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*
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* Atomically decrements @v by 1 and
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* returns true if the result is 0, or false for all other
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* cases.
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*/
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#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
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/*
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* atomic_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic_t
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*/
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#define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
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/*
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* atomic_inc - increment atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically increments @v by 1.
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*/
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#define atomic_inc(v) atomic_add(1,(v))
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/*
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* atomic_dec - decrement and test
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* @v: pointer of type atomic_t
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*
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* Atomically decrements @v by 1.
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*/
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#define atomic_dec(v) atomic_sub(1,(v))
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/*
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* atomic_add_negative - add and test if negative
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* @v: pointer of type atomic_t
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* @i: integer value to add
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*
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* Atomically adds @i to @v and returns true
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* if the result is negative, or false when
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* result is greater than or equal to zero.
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*/
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#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0)
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#ifdef CONFIG_64BIT
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typedef struct { volatile __s64 counter; } atomic64_t;
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#define ATOMIC64_INIT(i) { (i) }
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/*
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* atomic64_read - read atomic variable
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* @v: pointer of type atomic64_t
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*
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*/
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#define atomic64_read(v) ((v)->counter)
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/*
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* atomic64_set - set atomic variable
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* @v: pointer of type atomic64_t
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* @i: required value
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*/
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#define atomic64_set(v,i) ((v)->counter = (i))
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/*
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* atomic64_add - add integer to atomic variable
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* @i: integer value to add
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* @v: pointer of type atomic64_t
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*
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* Atomically adds @i to @v.
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*/
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static __inline__ void atomic64_add(long i, atomic64_t * v)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %1 # atomic64_add \n"
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" addu %0, %2 \n"
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" scd %0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter));
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} else if (cpu_has_llsc) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %1 # atomic64_add \n"
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" addu %0, %2 \n"
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" scd %0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter));
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} else {
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unsigned long flags;
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spin_lock_irqsave(&atomic_lock, flags);
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v->counter += i;
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spin_unlock_irqrestore(&atomic_lock, flags);
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}
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}
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/*
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* atomic64_sub - subtract the atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic64_t
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*
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* Atomically subtracts @i from @v.
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*/
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static __inline__ void atomic64_sub(long i, atomic64_t * v)
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{
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %1 # atomic64_sub \n"
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" subu %0, %2 \n"
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" scd %0, %1 \n"
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" beqzl %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter));
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} else if (cpu_has_llsc) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %0, %1 # atomic64_sub \n"
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" subu %0, %2 \n"
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" scd %0, %1 \n"
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" beqz %0, 1b \n"
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" .set mips0 \n"
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: "=&r" (temp), "=m" (v->counter)
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: "Ir" (i), "m" (v->counter));
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} else {
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unsigned long flags;
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spin_lock_irqsave(&atomic_lock, flags);
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v->counter -= i;
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spin_unlock_irqrestore(&atomic_lock, flags);
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}
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}
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/*
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* Same as above, but return the result value
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*/
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static __inline__ long atomic64_add_return(long i, atomic64_t * v)
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{
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unsigned long result;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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unsigned long temp;
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__asm__ __volatile__(
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" .set mips3 \n"
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"1: lld %1, %2 # atomic64_add_return \n"
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" addu %0, %1, %3 \n"
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" scd %0, %2 \n"
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" beqzl %0, 1b \n"
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" addu %0, %1, %3 \n"
|
|
" sync \n"
|
|
" .set mips0 \n"
|
|
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
|
|
: "Ir" (i), "m" (v->counter)
|
|
: "memory");
|
|
} else if (cpu_has_llsc) {
|
|
unsigned long temp;
|
|
|
|
__asm__ __volatile__(
|
|
" .set mips3 \n"
|
|
"1: lld %1, %2 # atomic64_add_return \n"
|
|
" addu %0, %1, %3 \n"
|
|
" scd %0, %2 \n"
|
|
" beqz %0, 1b \n"
|
|
" addu %0, %1, %3 \n"
|
|
" sync \n"
|
|
" .set mips0 \n"
|
|
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
|
|
: "Ir" (i), "m" (v->counter)
|
|
: "memory");
|
|
} else {
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&atomic_lock, flags);
|
|
result = v->counter;
|
|
result += i;
|
|
v->counter = result;
|
|
spin_unlock_irqrestore(&atomic_lock, flags);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
|
|
{
|
|
unsigned long result;
|
|
|
|
if (cpu_has_llsc && R10000_LLSC_WAR) {
|
|
unsigned long temp;
|
|
|
|
__asm__ __volatile__(
|
|
" .set mips3 \n"
|
|
"1: lld %1, %2 # atomic64_sub_return \n"
|
|
" subu %0, %1, %3 \n"
|
|
" scd %0, %2 \n"
|
|
" beqzl %0, 1b \n"
|
|
" subu %0, %1, %3 \n"
|
|
" sync \n"
|
|
" .set mips0 \n"
|
|
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
|
|
: "Ir" (i), "m" (v->counter)
|
|
: "memory");
|
|
} else if (cpu_has_llsc) {
|
|
unsigned long temp;
|
|
|
|
__asm__ __volatile__(
|
|
" .set mips3 \n"
|
|
"1: lld %1, %2 # atomic64_sub_return \n"
|
|
" subu %0, %1, %3 \n"
|
|
" scd %0, %2 \n"
|
|
" beqz %0, 1b \n"
|
|
" subu %0, %1, %3 \n"
|
|
" sync \n"
|
|
" .set mips0 \n"
|
|
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
|
|
: "Ir" (i), "m" (v->counter)
|
|
: "memory");
|
|
} else {
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&atomic_lock, flags);
|
|
result = v->counter;
|
|
result -= i;
|
|
v->counter = result;
|
|
spin_unlock_irqrestore(&atomic_lock, flags);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
/*
|
|
* atomic64_sub_if_positive - conditionally subtract integer from atomic variable
|
|
* @i: integer value to subtract
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically test @v and subtract @i if @v is greater or equal than @i.
|
|
* The function returns the old value of @v minus @i.
|
|
*/
|
|
static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
|
|
{
|
|
unsigned long result;
|
|
|
|
if (cpu_has_llsc && R10000_LLSC_WAR) {
|
|
unsigned long temp;
|
|
|
|
__asm__ __volatile__(
|
|
" .set mips3 \n"
|
|
"1: lld %1, %2 # atomic64_sub_if_positive\n"
|
|
" dsubu %0, %1, %3 \n"
|
|
" bltz %0, 1f \n"
|
|
" scd %0, %2 \n"
|
|
" beqzl %0, 1b \n"
|
|
" sync \n"
|
|
"1: \n"
|
|
" .set mips0 \n"
|
|
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
|
|
: "Ir" (i), "m" (v->counter)
|
|
: "memory");
|
|
} else if (cpu_has_llsc) {
|
|
unsigned long temp;
|
|
|
|
__asm__ __volatile__(
|
|
" .set mips3 \n"
|
|
"1: lld %1, %2 # atomic64_sub_if_positive\n"
|
|
" dsubu %0, %1, %3 \n"
|
|
" bltz %0, 1f \n"
|
|
" scd %0, %2 \n"
|
|
" beqz %0, 1b \n"
|
|
" sync \n"
|
|
"1: \n"
|
|
" .set mips0 \n"
|
|
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
|
|
: "Ir" (i), "m" (v->counter)
|
|
: "memory");
|
|
} else {
|
|
unsigned long flags;
|
|
|
|
spin_lock_irqsave(&atomic_lock, flags);
|
|
result = v->counter;
|
|
result -= i;
|
|
if (result >= 0)
|
|
v->counter = result;
|
|
spin_unlock_irqrestore(&atomic_lock, flags);
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
#define atomic64_dec_return(v) atomic64_sub_return(1,(v))
|
|
#define atomic64_inc_return(v) atomic64_add_return(1,(v))
|
|
|
|
/*
|
|
* atomic64_sub_and_test - subtract value from variable and test result
|
|
* @i: integer value to subtract
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically subtracts @i from @v and returns
|
|
* true if the result is zero, or false for all
|
|
* other cases.
|
|
*/
|
|
#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
|
|
|
|
/*
|
|
* atomic64_inc_and_test - increment and test
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically increments @v by 1
|
|
* and returns true if the result is zero, or false for all
|
|
* other cases.
|
|
*/
|
|
#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
|
|
|
|
/*
|
|
* atomic64_dec_and_test - decrement by 1 and test
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically decrements @v by 1 and
|
|
* returns true if the result is 0, or false for all other
|
|
* cases.
|
|
*/
|
|
#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
|
|
|
|
/*
|
|
* atomic64_dec_if_positive - decrement by 1 if old value positive
|
|
* @v: pointer of type atomic64_t
|
|
*/
|
|
#define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v)
|
|
|
|
/*
|
|
* atomic64_inc - increment atomic variable
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically increments @v by 1.
|
|
*/
|
|
#define atomic64_inc(v) atomic64_add(1,(v))
|
|
|
|
/*
|
|
* atomic64_dec - decrement and test
|
|
* @v: pointer of type atomic64_t
|
|
*
|
|
* Atomically decrements @v by 1.
|
|
*/
|
|
#define atomic64_dec(v) atomic64_sub(1,(v))
|
|
|
|
/*
|
|
* atomic64_add_negative - add and test if negative
|
|
* @v: pointer of type atomic64_t
|
|
* @i: integer value to add
|
|
*
|
|
* Atomically adds @i to @v and returns true
|
|
* if the result is negative, or false when
|
|
* result is greater than or equal to zero.
|
|
*/
|
|
#define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0)
|
|
|
|
#endif /* CONFIG_64BIT */
|
|
|
|
/*
|
|
* atomic*_return operations are serializing but not the non-*_return
|
|
* versions.
|
|
*/
|
|
#define smp_mb__before_atomic_dec() smp_mb()
|
|
#define smp_mb__after_atomic_dec() smp_mb()
|
|
#define smp_mb__before_atomic_inc() smp_mb()
|
|
#define smp_mb__after_atomic_inc() smp_mb()
|
|
|
|
#include <asm-generic/atomic.h>
|
|
#endif /* _ASM_ATOMIC_H */
|