acaca3c915
SVC_MODE reflects the MODE_SVC definition in asm/ptrace.h. Use the asm/ptrace.h definition instead, and remove SVC_MODE. Signed-off-by: Russell King <rmk@arm.linux.org.uk>
735 lines
16 KiB
ArmAsm
735 lines
16 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/entry-armv.S
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*
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* Copyright (C) 1996,1997,1998 Russell King.
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* ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Low-level vector interface routines
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*
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* Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction that causes
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* it to save wrong values... Be aware!
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <asm/thread_info.h>
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#include <asm/glue.h>
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#include <asm/ptrace.h>
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#include <asm/vfpmacros.h>
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#include "entry-header.S"
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/*
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* Invalid mode handlers
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*/
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.macro inv_entry, sym, reason
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sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
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stmia sp, {r0 - lr} @ Save XXX r0 - lr
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ldr r4, .LC\sym
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mov r1, #\reason
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.endm
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__pabt_invalid:
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inv_entry abt, BAD_PREFETCH
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b 1f
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__dabt_invalid:
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inv_entry abt, BAD_DATA
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b 1f
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__irq_invalid:
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inv_entry irq, BAD_IRQ
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b 1f
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__und_invalid:
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inv_entry und, BAD_UNDEFINSTR
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1: zero_fp
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ldmia r4, {r5 - r7} @ Get XXX pc, cpsr, old_r0
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add r4, sp, #S_PC
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stmia r4, {r5 - r7} @ Save XXX pc, cpsr, old_r0
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mov r0, sp
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and r2, r6, #31 @ int mode
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b bad_mode
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/*
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* SVC mode handlers
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*/
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.macro svc_entry, sym
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sub sp, sp, #S_FRAME_SIZE
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stmia sp, {r0 - r12} @ save r0 - r12
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ldr r2, .LC\sym
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add r0, sp, #S_FRAME_SIZE
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ldmia r2, {r2 - r4} @ get pc, cpsr
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add r5, sp, #S_SP
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mov r1, lr
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@
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@ We are now ready to fill in the remaining blanks on the stack:
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@
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@ r0 - sp_svc
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@ r1 - lr_svc
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@ r2 - lr_<exception>, already fixed up for correct return/restart
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@ r3 - spsr_<exception>
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@ r4 - orig_r0 (see pt_regs definition in ptrace.h)
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@
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stmia r5, {r0 - r4}
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.endm
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.align 5
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__dabt_svc:
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svc_entry abt
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@
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@ get ready to re-enable interrupts if appropriate
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@
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mrs r9, cpsr
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tst r3, #PSR_I_BIT
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biceq r9, r9, #PSR_I_BIT
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@
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@ Call the processor-specific abort handler:
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@
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@ r2 - aborted context pc
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@ r3 - aborted context cpsr
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@
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@ The abort handler must return the aborted address in r0, and
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@ the fault status register in r1. r9 must be preserved.
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@
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#ifdef MULTI_ABORT
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ldr r4, .LCprocfns
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mov lr, pc
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ldr pc, [r4]
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#else
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bl CPU_ABORT_HANDLER
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#endif
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@
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@ set desired IRQ state, then call main handler
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@
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msr cpsr_c, r9
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mov r2, sp
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bl do_DataAbort
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@
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@ IRQs off again before pulling preserved data off the stack
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@
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disable_irq
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@
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@ restore SPSR and restart the instruction
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@
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ldr r0, [sp, #S_PSR]
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msr spsr_cxsf, r0
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ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
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.align 5
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__irq_svc:
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svc_entry irq
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#ifdef CONFIG_PREEMPT
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get_thread_info r8
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ldr r9, [r8, #TI_PREEMPT] @ get preempt count
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add r7, r9, #1 @ increment it
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str r7, [r8, #TI_PREEMPT]
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#endif
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1: get_irqnr_and_base r0, r6, r5, lr
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movne r1, sp
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@
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@ routine called with r0 = irq number, r1 = struct pt_regs *
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@
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adrne lr, 1b
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bne asm_do_IRQ
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#ifdef CONFIG_PREEMPT
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ldr r0, [r8, #TI_FLAGS] @ get flags
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tst r0, #_TIF_NEED_RESCHED
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blne svc_preempt
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preempt_return:
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ldr r0, [r8, #TI_PREEMPT] @ read preempt value
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teq r0, r7
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str r9, [r8, #TI_PREEMPT] @ restore preempt count
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strne r0, [r0, -r0] @ bug()
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#endif
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ldr r0, [sp, #S_PSR] @ irqs are already disabled
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msr spsr_cxsf, r0
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ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
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.ltorg
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#ifdef CONFIG_PREEMPT
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svc_preempt:
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teq r9, #0 @ was preempt count = 0
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ldreq r6, .LCirq_stat
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movne pc, lr @ no
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ldr r0, [r6, #4] @ local_irq_count
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ldr r1, [r6, #8] @ local_bh_count
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adds r0, r0, r1
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movne pc, lr
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mov r7, #0 @ preempt_schedule_irq
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str r7, [r8, #TI_PREEMPT] @ expects preempt_count == 0
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1: bl preempt_schedule_irq @ irq en/disable is done inside
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ldr r0, [r8, #TI_FLAGS] @ get new tasks TI_FLAGS
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tst r0, #_TIF_NEED_RESCHED
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beq preempt_return @ go again
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b 1b
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#endif
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.align 5
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__und_svc:
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svc_entry und
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@
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@ call emulation code, which returns using r9 if it has emulated
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@ the instruction, or the more conventional lr if we are to treat
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@ this as a real undefined instruction
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@
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@ r0 - instruction
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@
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ldr r0, [r2, #-4]
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adr r9, 1f
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bl call_fpe
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mov r0, sp @ struct pt_regs *regs
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bl do_undefinstr
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@
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@ IRQs off again before pulling preserved data off the stack
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@
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1: disable_irq
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@
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@ restore SPSR and restart the instruction
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@
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ldr lr, [sp, #S_PSR] @ Get SVC cpsr
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msr spsr_cxsf, lr
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ldmia sp, {r0 - pc}^ @ Restore SVC registers
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.align 5
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__pabt_svc:
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svc_entry abt
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@
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@ re-enable interrupts if appropriate
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@
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mrs r9, cpsr
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tst r3, #PSR_I_BIT
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biceq r9, r9, #PSR_I_BIT
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msr cpsr_c, r9
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@
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@ set args, then call main handler
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@
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@ r0 - address of faulting instruction
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@ r1 - pointer to registers on stack
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@
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mov r0, r2 @ address (pc)
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mov r1, sp @ regs
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bl do_PrefetchAbort @ call abort handler
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@
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@ IRQs off again before pulling preserved data off the stack
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@
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disable_irq
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@
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@ restore SPSR and restart the instruction
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@
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ldr r0, [sp, #S_PSR]
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msr spsr_cxsf, r0
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ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
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.align 5
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.LCirq:
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.word __temp_irq
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.LCund:
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.word __temp_und
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.LCabt:
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.word __temp_abt
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#ifdef MULTI_ABORT
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.LCprocfns:
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.word processor
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#endif
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.LCfp:
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.word fp_enter
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#ifdef CONFIG_PREEMPT
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.LCirq_stat:
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.word irq_stat
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#endif
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/*
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* User mode handlers
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*/
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.macro usr_entry, sym
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sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
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stmia sp, {r0 - r12} @ save r0 - r12
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ldr r7, .LC\sym
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add r5, sp, #S_PC
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ldmia r7, {r2 - r4} @ Get USR pc, cpsr
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@
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@ We are now ready to fill in the remaining blanks on the stack:
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@
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@ r2 - lr_<exception>, already fixed up for correct return/restart
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@ r3 - spsr_<exception>
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@ r4 - orig_r0 (see pt_regs definition in ptrace.h)
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@
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@ Also, separately save sp_usr and lr_usr
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@
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stmia r5, {r2 - r4}
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stmdb r5, {sp, lr}^
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@
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@ Enable the alignment trap while in kernel mode
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@
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alignment_trap r7, r0, __temp_\sym
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@
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@ Clear FP to mark the first stack frame
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@
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zero_fp
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.endm
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.align 5
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__dabt_usr:
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usr_entry abt
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@
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@ Call the processor-specific abort handler:
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@
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@ r2 - aborted context pc
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@ r3 - aborted context cpsr
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@
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@ The abort handler must return the aborted address in r0, and
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@ the fault status register in r1.
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@
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#ifdef MULTI_ABORT
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ldr r4, .LCprocfns
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mov lr, pc
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ldr pc, [r4]
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#else
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bl CPU_ABORT_HANDLER
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#endif
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@
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@ IRQs on, then call the main handler
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@
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enable_irq
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mov r2, sp
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adr lr, ret_from_exception
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b do_DataAbort
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.align 5
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__irq_usr:
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usr_entry irq
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#ifdef CONFIG_PREEMPT
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get_thread_info r8
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ldr r9, [r8, #TI_PREEMPT] @ get preempt count
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add r7, r9, #1 @ increment it
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str r7, [r8, #TI_PREEMPT]
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#endif
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1: get_irqnr_and_base r0, r6, r5, lr
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movne r1, sp
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adrne lr, 1b
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@
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@ routine called with r0 = irq number, r1 = struct pt_regs *
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@
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bne asm_do_IRQ
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#ifdef CONFIG_PREEMPT
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ldr r0, [r8, #TI_PREEMPT]
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teq r0, r7
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str r9, [r8, #TI_PREEMPT]
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strne r0, [r0, -r0]
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mov tsk, r8
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#else
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get_thread_info tsk
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#endif
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mov why, #0
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b ret_to_user
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.ltorg
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.align 5
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__und_usr:
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usr_entry und
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tst r3, #PSR_T_BIT @ Thumb mode?
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bne fpundefinstr @ ignore FP
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sub r4, r2, #4
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@
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@ fall through to the emulation code, which returns using r9 if
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@ it has emulated the instruction, or the more conventional lr
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@ if we are to treat this as a real undefined instruction
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@
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@ r0 - instruction
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@
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1: ldrt r0, [r4]
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adr r9, ret_from_exception
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adr lr, fpundefinstr
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@
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@ fallthrough to call_fpe
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@
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/*
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* The out of line fixup for the ldrt above.
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*/
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.section .fixup, "ax"
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2: mov pc, r9
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.previous
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.section __ex_table,"a"
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.long 1b, 2b
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.previous
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/*
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* Check whether the instruction is a co-processor instruction.
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* If yes, we need to call the relevant co-processor handler.
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*
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* Note that we don't do a full check here for the co-processor
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* instructions; all instructions with bit 27 set are well
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* defined. The only instructions that should fault are the
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* co-processor instructions. However, we have to watch out
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* for the ARM6/ARM7 SWI bug.
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*
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* Emulators may wish to make use of the following registers:
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* r0 = instruction opcode.
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* r2 = PC+4
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* r10 = this threads thread_info structure.
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*/
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call_fpe:
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tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
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#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
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and r8, r0, #0x0f000000 @ mask out op-code bits
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teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
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#endif
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moveq pc, lr
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get_thread_info r10 @ get current thread
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and r8, r0, #0x00000f00 @ mask out CP number
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mov r7, #1
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add r6, r10, #TI_USED_CP
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strb r7, [r6, r8, lsr #8] @ set appropriate used_cp[]
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#ifdef CONFIG_IWMMXT
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@ Test if we need to give access to iWMMXt coprocessors
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ldr r5, [r10, #TI_FLAGS]
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rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
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movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
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bcs iwmmxt_task_enable
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#endif
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enable_irq
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add pc, pc, r8, lsr #6
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mov r0, r0
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mov pc, lr @ CP#0
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b do_fpe @ CP#1 (FPE)
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b do_fpe @ CP#2 (FPE)
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mov pc, lr @ CP#3
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mov pc, lr @ CP#4
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mov pc, lr @ CP#5
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mov pc, lr @ CP#6
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mov pc, lr @ CP#7
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mov pc, lr @ CP#8
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mov pc, lr @ CP#9
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#ifdef CONFIG_VFP
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b do_vfp @ CP#10 (VFP)
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b do_vfp @ CP#11 (VFP)
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#else
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mov pc, lr @ CP#10 (VFP)
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mov pc, lr @ CP#11 (VFP)
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#endif
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mov pc, lr @ CP#12
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mov pc, lr @ CP#13
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mov pc, lr @ CP#14 (Debug)
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mov pc, lr @ CP#15 (Control)
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do_fpe:
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ldr r4, .LCfp
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add r10, r10, #TI_FPSTATE @ r10 = workspace
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ldr pc, [r4] @ Call FP module USR entry point
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/*
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* The FP module is called with these registers set:
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* r0 = instruction
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* r2 = PC+4
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* r9 = normal "successful" return address
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* r10 = FP workspace
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* lr = unrecognised FP instruction return address
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*/
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.data
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ENTRY(fp_enter)
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.word fpundefinstr
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.text
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fpundefinstr:
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mov r0, sp
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adr lr, ret_from_exception
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b do_undefinstr
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.align 5
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__pabt_usr:
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usr_entry abt
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enable_irq @ Enable interrupts
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mov r0, r2 @ address (pc)
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mov r1, sp @ regs
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bl do_PrefetchAbort @ call abort handler
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/* fall through */
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/*
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* This is the return code to user mode for abort handlers
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*/
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ENTRY(ret_from_exception)
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get_thread_info tsk
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mov why, #0
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b ret_to_user
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/*
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* Register switch for ARMv3 and ARMv4 processors
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* r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
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* previous and next are guaranteed not to be the same.
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*/
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ENTRY(__switch_to)
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add ip, r1, #TI_CPU_SAVE
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ldr r3, [r2, #TI_TP_VALUE]
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stmia ip!, {r4 - sl, fp, sp, lr} @ Store most regs on stack
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ldr r6, [r2, #TI_CPU_DOMAIN]!
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#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
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mra r4, r5, acc0
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stmia ip, {r4, r5}
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#endif
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mov r4, #0xffff0fff
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str r3, [r4, #-3] @ Set TLS ptr
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mcr p15, 0, r6, c3, c0, 0 @ Set domain register
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#ifdef CONFIG_VFP
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@ Always disable VFP so we can lazily save/restore the old
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@ state. This occurs in the context of the previous thread.
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VFPFMRX r4, FPEXC
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bic r4, r4, #FPEXC_ENABLE
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VFPFMXR FPEXC, r4
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#endif
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#if defined(CONFIG_IWMMXT)
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bl iwmmxt_task_switch
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#elif defined(CONFIG_CPU_XSCALE)
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add r4, r2, #40 @ cpu_context_save->extra
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ldmib r4, {r4, r5}
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mar acc0, r4, r5
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#endif
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ldmib r2, {r4 - sl, fp, sp, pc} @ Load all regs saved previously
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__INIT
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/*
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* Vector stubs.
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*
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* This code is copied to 0xffff0200 so we can use branches in the
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* vectors, rather than ldr's. Note that this code must not
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* exceed 0x300 bytes.
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*
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* Common stub entry macro:
|
|
* Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
|
|
*/
|
|
.macro vector_stub, name, sym, correction=0
|
|
.align 5
|
|
|
|
vector_\name:
|
|
ldr r13, .LCs\sym
|
|
.if \correction
|
|
sub lr, lr, #\correction
|
|
.endif
|
|
str lr, [r13] @ save lr_IRQ
|
|
mrs lr, spsr
|
|
str lr, [r13, #4] @ save spsr_IRQ
|
|
@
|
|
@ now branch to the relevant MODE handling routine
|
|
@
|
|
mrs r13, cpsr
|
|
bic r13, r13, #MODE_MASK
|
|
orr r13, r13, #SVC_MODE
|
|
msr spsr_cxsf, r13 @ switch to SVC_32 mode
|
|
|
|
and lr, lr, #15
|
|
ldr lr, [pc, lr, lsl #2]
|
|
movs pc, lr @ Changes mode and branches
|
|
.endm
|
|
|
|
.globl __stubs_start
|
|
__stubs_start:
|
|
/*
|
|
* Interrupt dispatcher
|
|
*/
|
|
vector_stub irq, irq, 4
|
|
|
|
.long __irq_usr @ 0 (USR_26 / USR_32)
|
|
.long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
|
|
.long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
|
|
.long __irq_svc @ 3 (SVC_26 / SVC_32)
|
|
.long __irq_invalid @ 4
|
|
.long __irq_invalid @ 5
|
|
.long __irq_invalid @ 6
|
|
.long __irq_invalid @ 7
|
|
.long __irq_invalid @ 8
|
|
.long __irq_invalid @ 9
|
|
.long __irq_invalid @ a
|
|
.long __irq_invalid @ b
|
|
.long __irq_invalid @ c
|
|
.long __irq_invalid @ d
|
|
.long __irq_invalid @ e
|
|
.long __irq_invalid @ f
|
|
|
|
/*
|
|
* Data abort dispatcher
|
|
* Enter in ABT mode, spsr = USR CPSR, lr = USR PC
|
|
*/
|
|
vector_stub dabt, abt, 8
|
|
|
|
.long __dabt_usr @ 0 (USR_26 / USR_32)
|
|
.long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
|
|
.long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
|
|
.long __dabt_svc @ 3 (SVC_26 / SVC_32)
|
|
.long __dabt_invalid @ 4
|
|
.long __dabt_invalid @ 5
|
|
.long __dabt_invalid @ 6
|
|
.long __dabt_invalid @ 7
|
|
.long __dabt_invalid @ 8
|
|
.long __dabt_invalid @ 9
|
|
.long __dabt_invalid @ a
|
|
.long __dabt_invalid @ b
|
|
.long __dabt_invalid @ c
|
|
.long __dabt_invalid @ d
|
|
.long __dabt_invalid @ e
|
|
.long __dabt_invalid @ f
|
|
|
|
/*
|
|
* Prefetch abort dispatcher
|
|
* Enter in ABT mode, spsr = USR CPSR, lr = USR PC
|
|
*/
|
|
vector_stub pabt, abt, 4
|
|
|
|
.long __pabt_usr @ 0 (USR_26 / USR_32)
|
|
.long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
|
|
.long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
|
|
.long __pabt_svc @ 3 (SVC_26 / SVC_32)
|
|
.long __pabt_invalid @ 4
|
|
.long __pabt_invalid @ 5
|
|
.long __pabt_invalid @ 6
|
|
.long __pabt_invalid @ 7
|
|
.long __pabt_invalid @ 8
|
|
.long __pabt_invalid @ 9
|
|
.long __pabt_invalid @ a
|
|
.long __pabt_invalid @ b
|
|
.long __pabt_invalid @ c
|
|
.long __pabt_invalid @ d
|
|
.long __pabt_invalid @ e
|
|
.long __pabt_invalid @ f
|
|
|
|
/*
|
|
* Undef instr entry dispatcher
|
|
* Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
|
|
*/
|
|
vector_stub und, und
|
|
|
|
.long __und_usr @ 0 (USR_26 / USR_32)
|
|
.long __und_invalid @ 1 (FIQ_26 / FIQ_32)
|
|
.long __und_invalid @ 2 (IRQ_26 / IRQ_32)
|
|
.long __und_svc @ 3 (SVC_26 / SVC_32)
|
|
.long __und_invalid @ 4
|
|
.long __und_invalid @ 5
|
|
.long __und_invalid @ 6
|
|
.long __und_invalid @ 7
|
|
.long __und_invalid @ 8
|
|
.long __und_invalid @ 9
|
|
.long __und_invalid @ a
|
|
.long __und_invalid @ b
|
|
.long __und_invalid @ c
|
|
.long __und_invalid @ d
|
|
.long __und_invalid @ e
|
|
.long __und_invalid @ f
|
|
|
|
.align 5
|
|
|
|
/*=============================================================================
|
|
* Undefined FIQs
|
|
*-----------------------------------------------------------------------------
|
|
* Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
|
|
* MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
|
|
* Basically to switch modes, we *HAVE* to clobber one register... brain
|
|
* damage alert! I don't think that we can execute any code in here in any
|
|
* other mode than FIQ... Ok you can switch to another mode, but you can't
|
|
* get out of that mode without clobbering one register.
|
|
*/
|
|
vector_fiq:
|
|
disable_fiq
|
|
subs pc, lr, #4
|
|
|
|
/*=============================================================================
|
|
* Address exception handler
|
|
*-----------------------------------------------------------------------------
|
|
* These aren't too critical.
|
|
* (they're not supposed to happen, and won't happen in 32-bit data mode).
|
|
*/
|
|
|
|
vector_addrexcptn:
|
|
b vector_addrexcptn
|
|
|
|
/*
|
|
* We group all the following data together to optimise
|
|
* for CPUs with separate I & D caches.
|
|
*/
|
|
.align 5
|
|
|
|
.LCvswi:
|
|
.word vector_swi
|
|
|
|
.LCsirq:
|
|
.word __temp_irq
|
|
.LCsund:
|
|
.word __temp_und
|
|
.LCsabt:
|
|
.word __temp_abt
|
|
|
|
.globl __stubs_end
|
|
__stubs_end:
|
|
|
|
.equ stubs_offset, __vectors_start + 0x200 - __stubs_start
|
|
|
|
.globl __vectors_start
|
|
__vectors_start:
|
|
swi SYS_ERROR0
|
|
b vector_und + stubs_offset
|
|
ldr pc, .LCvswi + stubs_offset
|
|
b vector_pabt + stubs_offset
|
|
b vector_dabt + stubs_offset
|
|
b vector_addrexcptn + stubs_offset
|
|
b vector_irq + stubs_offset
|
|
b vector_fiq + stubs_offset
|
|
|
|
.globl __vectors_end
|
|
__vectors_end:
|
|
|
|
.data
|
|
|
|
/*
|
|
* Do not reorder these, and do not insert extra data between...
|
|
*/
|
|
|
|
__temp_irq:
|
|
.word 0 @ saved lr_irq
|
|
.word 0 @ saved spsr_irq
|
|
.word -1 @ old_r0
|
|
__temp_und:
|
|
.word 0 @ Saved lr_und
|
|
.word 0 @ Saved spsr_und
|
|
.word -1 @ old_r0
|
|
__temp_abt:
|
|
.word 0 @ Saved lr_abt
|
|
.word 0 @ Saved spsr_abt
|
|
.word -1 @ old_r0
|
|
|
|
.globl cr_alignment
|
|
.globl cr_no_alignment
|
|
cr_alignment:
|
|
.space 4
|
|
cr_no_alignment:
|
|
.space 4
|