ae78fd954b
Video kernel snapshot before disabling msm/vidc compilation from base kernel. Change-Id: Id1178c3aca00706ad4822537f7f9a28141478771 Signed-off-by: Shivendra Kakrania <shiven@codeaurora.org>
412 lines
13 KiB
C
412 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#include "msm_vidc_debug.h"
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#include "hfi_common.h"
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#define VBIF_BASE_OFFS_IRIS2 0x00080000
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#define CPU_BASE_OFFS_IRIS2 0x000A0000
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#define AON_BASE_OFFS 0x000E0000
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#define CPU_CS_BASE_OFFS_IRIS2 (CPU_BASE_OFFS_IRIS2)
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#define CPU_IC_BASE_OFFS_IRIS2 (CPU_BASE_OFFS_IRIS2)
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#define CPU_CS_A2HSOFTINTCLR_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x1C)
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#define CPU_CS_VMIMSG_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x34)
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#define CPU_CS_VMIMSGAG0_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x38)
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#define CPU_CS_VMIMSGAG1_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x3C)
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#define CPU_CS_SCIACMD_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x48)
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#define CPU_CS_H2XSOFTINTEN_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x148)
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/* HFI_CTRL_STATUS */
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#define CPU_CS_SCIACMDARG0_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x4C)
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#define CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK_IRIS2 0xfe
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#define CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY_IRIS2 0x100
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#define CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK_IRIS2 0x40000000
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/* HFI_QTBL_INFO */
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#define CPU_CS_SCIACMDARG1_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x50)
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/* HFI_QTBL_ADDR */
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#define CPU_CS_SCIACMDARG2_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x54)
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/* HFI_VERSION_INFO */
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#define CPU_CS_SCIACMDARG3_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x58)
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/* SFR_ADDR */
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#define CPU_CS_SCIBCMD_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x5C)
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/* MMAP_ADDR */
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#define CPU_CS_SCIBCMDARG0_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x60)
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/* UC_REGION_ADDR */
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#define CPU_CS_SCIBARG1_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x64)
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/* UC_REGION_ADDR */
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#define CPU_CS_SCIBARG2_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x68)
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/* FAL10 Feature Control */
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#define CPU_CS_X2RPMh_IRIS2 (CPU_CS_BASE_OFFS_IRIS2 + 0x168)
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#define CPU_CS_X2RPMh_MASK0_BMSK_IRIS2 0x1
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#define CPU_CS_X2RPMh_MASK0_SHFT_IRIS2 0x0
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#define CPU_CS_X2RPMh_MASK1_BMSK_IRIS2 0x2
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#define CPU_CS_X2RPMh_MASK1_SHFT_IRIS2 0x1
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#define CPU_CS_X2RPMh_SWOVERRIDE_BMSK_IRIS2 0x4
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#define CPU_CS_X2RPMh_SWOVERRIDE_SHFT_IRIS2 0x3
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#define CPU_IC_SOFTINT_IRIS2 (CPU_IC_BASE_OFFS_IRIS2 + 0x150)
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#define CPU_IC_SOFTINT_H2A_SHFT_IRIS2 0x0
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/*
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* --------------------------------------------------------------------------
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* MODULE: wrapper
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* --------------------------------------------------------------------------
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*/
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#define WRAPPER_BASE_OFFS_IRIS2 0x000B0000
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#define WRAPPER_INTR_STATUS_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x0C)
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#define WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS2 0x8
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#define WRAPPER_INTR_STATUS_A2H_BMSK_IRIS2 0x4
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#define WRAPPER_INTR_MASK_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x10)
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#define WRAPPER_INTR_MASK_A2HWD_BMSK_IRIS2 0x8
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#define WRAPPER_INTR_MASK_A2HCPU_BMSK_IRIS2 0x4
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#define WRAPPER_CPU_CLOCK_CONFIG_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x2000)
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#define WRAPPER_CPU_CGC_DIS_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x2010)
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#define WRAPPER_CPU_STATUS_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x2014)
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#define WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x54)
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#define WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS2 (WRAPPER_BASE_OFFS_IRIS2 + 0x58)
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/*
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* --------------------------------------------------------------------------
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* MODULE: tz_wrapper
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* --------------------------------------------------------------------------
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*/
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#define WRAPPER_TZ_BASE_OFFS 0x000C0000
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#define WRAPPER_TZ_CPU_CLOCK_CONFIG (WRAPPER_TZ_BASE_OFFS)
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#define WRAPPER_TZ_CPU_STATUS (WRAPPER_TZ_BASE_OFFS + 0x10)
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#define CTRL_INIT_IRIS2 CPU_CS_SCIACMD_IRIS2
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#define CTRL_STATUS_IRIS2 CPU_CS_SCIACMDARG0_IRIS2
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#define CTRL_ERROR_STATUS__M_IRIS2 \
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CPU_CS_SCIACMDARG0_HFI_CTRL_ERROR_STATUS_BMSK_IRIS2
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#define CTRL_INIT_IDLE_MSG_BMSK_IRIS2 \
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CPU_CS_SCIACMDARG0_HFI_CTRL_INIT_IDLE_MSG_BMSK_IRIS2
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#define CTRL_STATUS_PC_READY_IRIS2 \
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CPU_CS_SCIACMDARG0_HFI_CTRL_PC_READY_IRIS2
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#define QTBL_INFO_IRIS2 CPU_CS_SCIACMDARG1_IRIS2
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#define QTBL_ADDR_IRIS2 CPU_CS_SCIACMDARG2_IRIS2
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#define VERSION_INFO_IRIS2 CPU_CS_SCIACMDARG3_IRIS2
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#define SFR_ADDR_IRIS2 CPU_CS_SCIBCMD_IRIS2
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#define MMAP_ADDR_IRIS2 CPU_CS_SCIBCMDARG0_IRIS2
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#define UC_REGION_ADDR_IRIS2 CPU_CS_SCIBARG1_IRIS2
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#define UC_REGION_SIZE_IRIS2 CPU_CS_SCIBARG2_IRIS2
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#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS)
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#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4)
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/*
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* --------------------------------------------------------------------------
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* MODULE: vcodec noc error log registers (iris2)
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* --------------------------------------------------------------------------
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*/
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#define VCODEC_NOC_VIDEO_A_NOC_BASE_OFFS 0x00010000
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#define VCODEC_NOC_ERL_MAIN_SWID_LOW 0x00011200
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#define VCODEC_NOC_ERL_MAIN_SWID_HIGH 0x00011204
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#define VCODEC_NOC_ERL_MAIN_MAINCTL_LOW 0x00011208
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#define VCODEC_NOC_ERL_MAIN_ERRVLD_LOW 0x00011210
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#define VCODEC_NOC_ERL_MAIN_ERRCLR_LOW 0x00011218
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#define VCODEC_NOC_ERL_MAIN_ERRLOG0_LOW 0x00011220
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#define VCODEC_NOC_ERL_MAIN_ERRLOG0_HIGH 0x00011224
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#define VCODEC_NOC_ERL_MAIN_ERRLOG1_LOW 0x00011228
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#define VCODEC_NOC_ERL_MAIN_ERRLOG1_HIGH 0x0001122C
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#define VCODEC_NOC_ERL_MAIN_ERRLOG2_LOW 0x00011230
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#define VCODEC_NOC_ERL_MAIN_ERRLOG2_HIGH 0x00011234
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#define VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW 0x00011238
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#define VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH 0x0001123C
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void __interrupt_init_iris2(struct venus_hfi_device *device)
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{
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u32 mask_val = 0;
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/* All interrupts should be disabled initially 0x1F6 : Reset value */
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mask_val = __read_register(device, WRAPPER_INTR_MASK_IRIS2);
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/* Write 0 to unmask CPU and WD interrupts */
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mask_val &= ~(WRAPPER_INTR_MASK_A2HWD_BMSK_IRIS2|
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WRAPPER_INTR_MASK_A2HCPU_BMSK_IRIS2);
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__write_register(device, WRAPPER_INTR_MASK_IRIS2, mask_val);
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}
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void __setup_ucregion_memory_map_iris2(struct venus_hfi_device *device)
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{
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__write_register(device, UC_REGION_ADDR_IRIS2,
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(u32)device->iface_q_table.align_device_addr);
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__write_register(device, UC_REGION_SIZE_IRIS2, SHARED_QSIZE);
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__write_register(device, QTBL_ADDR_IRIS2,
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(u32)device->iface_q_table.align_device_addr);
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__write_register(device, QTBL_INFO_IRIS2, 0x01);
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if (device->sfr.align_device_addr)
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__write_register(device, SFR_ADDR_IRIS2,
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(u32)device->sfr.align_device_addr);
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if (device->qdss.align_device_addr)
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__write_register(device, MMAP_ADDR_IRIS2,
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(u32)device->qdss.align_device_addr);
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}
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void __power_off_iris2(struct venus_hfi_device *device)
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{
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u32 lpi_status, reg_status = 0, count = 0, max_count = 10;
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if (!device->power_enabled)
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return;
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if (!(device->intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS2))
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disable_irq_nosync(device->hal_data->irq);
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device->intr_status = 0;
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/* HPG 6.1.2 Step 1 */
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__write_register(device, CPU_CS_X2RPMh_IRIS2, 0x3);
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/* HPG 6.1.2 Step 2, noc to low power */
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__write_register(device, AON_WRAPPER_MVP_NOC_LPI_CONTROL, 0x1);
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while (!reg_status && count < max_count) {
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lpi_status =
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__read_register(device,
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AON_WRAPPER_MVP_NOC_LPI_STATUS);
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reg_status = lpi_status & BIT(0);
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dprintk(VIDC_DBG,
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"Noc: lpi_status %d noc_status %d (count %d)\n",
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lpi_status, reg_status, count);
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usleep_range(50, 100);
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count++;
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}
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if (count == max_count) {
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dprintk(VIDC_ERR,
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"NOC not in qaccept status %d\n", reg_status);
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}
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/* HPG 6.1.2 Step 3, debug bridge to low power */
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__write_register(device,
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WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2, 0x7);
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reg_status = 0;
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count = 0;
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while ((reg_status != 0x7) && count < max_count) {
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lpi_status = __read_register(device,
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WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS2);
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reg_status = lpi_status & 0x7;
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dprintk(VIDC_DBG,
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"DBLP Set : lpi_status %d reg_status %d (count %d)\n",
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lpi_status, reg_status, count);
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usleep_range(50, 100);
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count++;
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}
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if (count == max_count) {
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dprintk(VIDC_ERR,
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"DBLP Set: status %d\n", reg_status);
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}
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/* HPG 6.1.2 Step 4, debug bridge to lpi release */
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__write_register(device,
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WRAPPER_DEBUG_BRIDGE_LPI_CONTROL_IRIS2, 0x0);
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lpi_status = 0x1;
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count = 0;
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while (lpi_status && count < max_count) {
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lpi_status = __read_register(device,
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WRAPPER_DEBUG_BRIDGE_LPI_STATUS_IRIS2);
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dprintk(VIDC_DBG,
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"DBLP Release: lpi_status %d(count %d)\n",
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lpi_status, count);
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usleep_range(50, 100);
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count++;
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}
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if (count == max_count) {
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dprintk(VIDC_ERR,
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"DBLP Release: lpi_status %d\n", lpi_status);
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}
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/* HPG 6.1.2 Step 6 */
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__disable_unprepare_clks(device);
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/* HPG 6.1.2 Step 7 & 8 */
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if (call_venus_op(device, reset_ahb2axi_bridge, device))
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dprintk(VIDC_ERR, "Failed to reset ahb2axi\n");
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/* HPG 6.1.2 Step 5 */
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if (__disable_regulators(device))
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dprintk(VIDC_WARN, "Failed to disable regulators\n");
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if (__unvote_buses(device))
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dprintk(VIDC_WARN, "Failed to unvote for buses\n");
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device->power_enabled = false;
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}
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int __prepare_pc_iris2(struct venus_hfi_device *device)
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{
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int rc = 0;
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u32 wfi_status = 0, idle_status = 0, pc_ready = 0;
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u32 ctrl_status = 0;
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int count = 0;
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const int max_tries = 10;
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ctrl_status = __read_register(device, CTRL_STATUS_IRIS2);
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pc_ready = ctrl_status & CTRL_STATUS_PC_READY_IRIS2;
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idle_status = ctrl_status & BIT(30);
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if (pc_ready) {
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dprintk(VIDC_DBG, "Already in pc_ready state\n");
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return 0;
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}
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wfi_status = BIT(0) & __read_register(device,
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WRAPPER_TZ_CPU_STATUS);
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if (!wfi_status || !idle_status) {
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dprintk(VIDC_WARN, "Skipping PC, wfi status not set\n");
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goto skip_power_off;
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}
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rc = __prepare_pc(device);
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if (rc) {
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dprintk(VIDC_WARN, "Failed __prepare_pc %d\n", rc);
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goto skip_power_off;
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}
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while (count < max_tries) {
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wfi_status = BIT(0) & __read_register(device,
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WRAPPER_TZ_CPU_STATUS);
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ctrl_status = __read_register(device, CTRL_STATUS_IRIS2);
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if (wfi_status && (ctrl_status & CTRL_STATUS_PC_READY_IRIS2))
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break;
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usleep_range(150, 250);
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count++;
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}
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if (count == max_tries) {
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dprintk(VIDC_ERR, "Skip PC. Core is not in right state\n");
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goto skip_power_off;
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}
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return rc;
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skip_power_off:
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dprintk(VIDC_WARN, "Skip PC, wfi=%#x, idle=%#x, pcr=%#x, ctrl=%#x)\n",
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wfi_status, idle_status, pc_ready, ctrl_status);
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return -EAGAIN;
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}
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void __raise_interrupt_iris2(struct venus_hfi_device *device)
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{
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__write_register(device, CPU_IC_SOFTINT_IRIS2,
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1 << CPU_IC_SOFTINT_H2A_SHFT_IRIS2);
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}
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bool __watchdog_iris2(u32 intr_status)
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{
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bool rc = false;
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if (intr_status & WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS2)
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rc = true;
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return rc;
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}
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void __noc_error_info_iris2(struct venus_hfi_device *device)
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{
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u32 val = 0;
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_SWID_LOW);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_SWID_LOW: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_SWID_HIGH);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_SWID_HIGH: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_MAINCTL_LOW);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_MAINCTL_LOW: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRVLD_LOW);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRVLD_LOW: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRCLR_LOW);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRCLR_LOW: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRLOG0_LOW);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRLOG0_LOW: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRLOG0_HIGH);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRLOG0_HIGH: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRLOG1_LOW);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRLOG1_LOW: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRLOG1_HIGH);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRLOG1_HIGH: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRLOG2_LOW);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRLOG2_LOW: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRLOG2_HIGH);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRLOG2_HIGH: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRLOG3_LOW: %#x\n", val);
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val = __read_register(device, VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH);
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dprintk(VIDC_ERR, "VCODEC_NOC_ERL_MAIN_ERRLOG3_HIGH: %#x\n", val);
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}
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void __core_clear_interrupt_iris2(struct venus_hfi_device *device)
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{
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u32 intr_status = 0, mask = 0;
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if (!device) {
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dprintk(VIDC_ERR, "%s: NULL device\n", __func__);
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return;
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}
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intr_status = __read_register(device, WRAPPER_INTR_STATUS_IRIS2);
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mask = (WRAPPER_INTR_STATUS_A2H_BMSK_IRIS2|
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WRAPPER_INTR_STATUS_A2HWD_BMSK_IRIS2|
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CTRL_INIT_IDLE_MSG_BMSK_IRIS2);
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if (intr_status & mask) {
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device->intr_status |= intr_status;
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device->reg_count++;
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dprintk(VIDC_DBG,
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"INTERRUPT for device: %pK: times: %d interrupt_status: %d\n",
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device, device->reg_count, intr_status);
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} else {
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device->spur_count++;
|
|
}
|
|
|
|
__write_register(device, CPU_CS_A2HSOFTINTCLR_IRIS2, 1);
|
|
}
|
|
|
|
int __boot_firmware_iris2(struct venus_hfi_device *device)
|
|
{
|
|
int rc = 0;
|
|
u32 ctrl_init_val = 0, ctrl_status = 0, count = 0, max_tries = 10000;
|
|
|
|
ctrl_init_val = BIT(0);
|
|
if (device->res->domain_cvp)
|
|
ctrl_init_val |= BIT(1);
|
|
|
|
__write_register(device, CTRL_INIT_IRIS2, ctrl_init_val);
|
|
while (!ctrl_status && count < max_tries) {
|
|
ctrl_status = __read_register(device, CTRL_STATUS_IRIS2);
|
|
if ((ctrl_status & CTRL_ERROR_STATUS__M_IRIS2) == 0x4) {
|
|
dprintk(VIDC_ERR, "invalid setting for UC_REGION\n");
|
|
break;
|
|
}
|
|
|
|
usleep_range(50, 100);
|
|
count++;
|
|
}
|
|
|
|
if (count >= max_tries) {
|
|
dprintk(VIDC_ERR, "Error booting up vidc firmware\n");
|
|
rc = -ETIME;
|
|
}
|
|
|
|
/* Enable interrupt before sending commands to venus */
|
|
__write_register(device, CPU_CS_H2XSOFTINTEN_IRIS2, 0x1);
|
|
__write_register(device, CPU_CS_X2RPMh_IRIS2, 0x0);
|
|
|
|
return rc;
|
|
}
|