ff3a3e9ba5
Signed-off-by: Pekka Paalanen <pq@iki.fi> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
490 lines
9.9 KiB
C
490 lines
9.9 KiB
C
/*
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* Fault Injection Test harness (FI)
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* Copyright (C) Intel Crop.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
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* USA.
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*
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*/
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/* Id: pf_in.c,v 1.1.1.1 2002/11/12 05:56:32 brlock Exp
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* Copyright by Intel Crop., 2002
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* Louis Zhuang (louis.zhuang@intel.com)
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*
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* Bjorn Steinbrink (B.Steinbrink@gmx.de), 2007
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*/
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#include <linux/module.h>
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#include <linux/ptrace.h> /* struct pt_regs */
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#include "pf_in.h"
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#ifdef __i386__
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/* IA32 Manual 3, 2-1 */
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static unsigned char prefix_codes[] = {
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0xF0, 0xF2, 0xF3, 0x2E, 0x36, 0x3E, 0x26, 0x64,
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0x65, 0x2E, 0x3E, 0x66, 0x67
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};
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/* IA32 Manual 3, 3-432*/
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static unsigned int reg_rop[] = {
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0x8A, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
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};
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static unsigned int reg_wop[] = { 0x88, 0x89 };
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static unsigned int imm_wop[] = { 0xC6, 0xC7 };
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/* IA32 Manual 3, 3-432*/
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static unsigned int rw8[] = { 0x88, 0x8A, 0xC6 };
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static unsigned int rw32[] = {
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0x89, 0x8B, 0xC7, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
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};
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static unsigned int mw8[] = { 0x88, 0x8A, 0xC6, 0xB60F, 0xBE0F };
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static unsigned int mw16[] = { 0xB70F, 0xBF0F };
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static unsigned int mw32[] = { 0x89, 0x8B, 0xC7 };
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static unsigned int mw64[] = {};
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#else /* not __i386__ */
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static unsigned char prefix_codes[] = {
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0x66, 0x67, 0x2E, 0x3E, 0x26, 0x64, 0x65, 0x36,
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0xF0, 0xF3, 0xF2,
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/* REX Prefixes */
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0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
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0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f
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};
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/* AMD64 Manual 3, Appendix A*/
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static unsigned int reg_rop[] = {
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0x8A, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
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};
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static unsigned int reg_wop[] = { 0x88, 0x89 };
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static unsigned int imm_wop[] = { 0xC6, 0xC7 };
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static unsigned int rw8[] = { 0xC6, 0x88, 0x8A };
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static unsigned int rw32[] = {
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0xC7, 0x89, 0x8B, 0xB60F, 0xB70F, 0xBE0F, 0xBF0F
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};
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/* 8 bit only */
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static unsigned int mw8[] = { 0xC6, 0x88, 0x8A, 0xB60F, 0xBE0F };
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/* 16 bit only */
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static unsigned int mw16[] = { 0xB70F, 0xBF0F };
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/* 16 or 32 bit */
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static unsigned int mw32[] = { 0xC7 };
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/* 16, 32 or 64 bit */
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static unsigned int mw64[] = { 0x89, 0x8B };
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#endif /* not __i386__ */
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static int skip_prefix(unsigned char *addr, int *shorted, int *enlarged,
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int *rexr)
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{
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int i;
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unsigned char *p = addr;
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*shorted = 0;
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*enlarged = 0;
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*rexr = 0;
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restart:
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for (i = 0; i < ARRAY_SIZE(prefix_codes); i++) {
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if (*p == prefix_codes[i]) {
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if (*p == 0x66)
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*shorted = 1;
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#ifdef __amd64__
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if ((*p & 0xf8) == 0x48)
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*enlarged = 1;
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if ((*p & 0xf4) == 0x44)
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*rexr = 1;
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#endif
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p++;
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goto restart;
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}
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}
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return (p - addr);
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}
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static int get_opcode(unsigned char *addr, unsigned int *opcode)
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{
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int len;
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if (*addr == 0x0F) {
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/* 0x0F is extension instruction */
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*opcode = *(unsigned short *)addr;
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len = 2;
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} else {
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*opcode = *addr;
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len = 1;
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}
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return len;
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}
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#define CHECK_OP_TYPE(opcode, array, type) \
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for (i = 0; i < ARRAY_SIZE(array); i++) { \
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if (array[i] == opcode) { \
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rv = type; \
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goto exit; \
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} \
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}
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enum reason_type get_ins_type(unsigned long ins_addr)
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{
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unsigned int opcode;
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unsigned char *p;
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int shorted, enlarged, rexr;
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int i;
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enum reason_type rv = OTHERS;
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p = (unsigned char *)ins_addr;
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p += skip_prefix(p, &shorted, &enlarged, &rexr);
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p += get_opcode(p, &opcode);
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CHECK_OP_TYPE(opcode, reg_rop, REG_READ);
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CHECK_OP_TYPE(opcode, reg_wop, REG_WRITE);
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CHECK_OP_TYPE(opcode, imm_wop, IMM_WRITE);
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exit:
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return rv;
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}
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#undef CHECK_OP_TYPE
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static unsigned int get_ins_reg_width(unsigned long ins_addr)
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{
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unsigned int opcode;
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unsigned char *p;
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int i, shorted, enlarged, rexr;
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p = (unsigned char *)ins_addr;
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p += skip_prefix(p, &shorted, &enlarged, &rexr);
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p += get_opcode(p, &opcode);
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for (i = 0; i < ARRAY_SIZE(rw8); i++)
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if (rw8[i] == opcode)
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return 1;
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for (i = 0; i < ARRAY_SIZE(rw32); i++)
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if (rw32[i] == opcode)
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return (shorted ? 2 : (enlarged ? 8 : 4));
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printk(KERN_ERR "mmiotrace: Unknown opcode 0x%02x\n", opcode);
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return 0;
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}
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unsigned int get_ins_mem_width(unsigned long ins_addr)
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{
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unsigned int opcode;
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unsigned char *p;
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int i, shorted, enlarged, rexr;
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p = (unsigned char *)ins_addr;
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p += skip_prefix(p, &shorted, &enlarged, &rexr);
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p += get_opcode(p, &opcode);
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for (i = 0; i < ARRAY_SIZE(mw8); i++)
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if (mw8[i] == opcode)
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return 1;
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for (i = 0; i < ARRAY_SIZE(mw16); i++)
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if (mw16[i] == opcode)
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return 2;
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for (i = 0; i < ARRAY_SIZE(mw32); i++)
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if (mw32[i] == opcode)
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return shorted ? 2 : 4;
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for (i = 0; i < ARRAY_SIZE(mw64); i++)
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if (mw64[i] == opcode)
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return shorted ? 2 : (enlarged ? 8 : 4);
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printk(KERN_ERR "mmiotrace: Unknown opcode 0x%02x\n", opcode);
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return 0;
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}
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/*
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* Define register ident in mod/rm byte.
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* Note: these are NOT the same as in ptrace-abi.h.
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*/
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enum {
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arg_AL = 0,
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arg_CL = 1,
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arg_DL = 2,
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arg_BL = 3,
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arg_AH = 4,
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arg_CH = 5,
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arg_DH = 6,
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arg_BH = 7,
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arg_AX = 0,
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arg_CX = 1,
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arg_DX = 2,
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arg_BX = 3,
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arg_SP = 4,
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arg_BP = 5,
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arg_SI = 6,
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arg_DI = 7,
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#ifdef __amd64__
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arg_R8 = 8,
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arg_R9 = 9,
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arg_R10 = 10,
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arg_R11 = 11,
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arg_R12 = 12,
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arg_R13 = 13,
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arg_R14 = 14,
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arg_R15 = 15
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#endif
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};
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static unsigned char *get_reg_w8(int no, struct pt_regs *regs)
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{
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unsigned char *rv = NULL;
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switch (no) {
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case arg_AL:
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rv = (unsigned char *)®s->ax;
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break;
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case arg_BL:
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rv = (unsigned char *)®s->bx;
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break;
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case arg_CL:
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rv = (unsigned char *)®s->cx;
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break;
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case arg_DL:
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rv = (unsigned char *)®s->dx;
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break;
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case arg_AH:
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rv = 1 + (unsigned char *)®s->ax;
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break;
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case arg_BH:
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rv = 1 + (unsigned char *)®s->bx;
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break;
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case arg_CH:
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rv = 1 + (unsigned char *)®s->cx;
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break;
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case arg_DH:
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rv = 1 + (unsigned char *)®s->dx;
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break;
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#ifdef __amd64__
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case arg_R8:
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rv = (unsigned char *)®s->r8;
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break;
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case arg_R9:
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rv = (unsigned char *)®s->r9;
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break;
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case arg_R10:
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rv = (unsigned char *)®s->r10;
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break;
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case arg_R11:
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rv = (unsigned char *)®s->r11;
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break;
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case arg_R12:
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rv = (unsigned char *)®s->r12;
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break;
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case arg_R13:
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rv = (unsigned char *)®s->r13;
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break;
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case arg_R14:
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rv = (unsigned char *)®s->r14;
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break;
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case arg_R15:
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rv = (unsigned char *)®s->r15;
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break;
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#endif
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default:
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printk(KERN_ERR "mmiotrace: Error reg no# %d\n", no);
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break;
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}
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return rv;
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}
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static unsigned long *get_reg_w32(int no, struct pt_regs *regs)
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{
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unsigned long *rv = NULL;
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switch (no) {
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case arg_AX:
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rv = ®s->ax;
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break;
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case arg_BX:
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rv = ®s->bx;
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break;
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case arg_CX:
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rv = ®s->cx;
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break;
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case arg_DX:
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rv = ®s->dx;
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break;
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case arg_SP:
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rv = ®s->sp;
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break;
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case arg_BP:
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rv = ®s->bp;
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break;
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case arg_SI:
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rv = ®s->si;
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break;
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case arg_DI:
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rv = ®s->di;
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break;
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#ifdef __amd64__
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case arg_R8:
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rv = ®s->r8;
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break;
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case arg_R9:
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rv = ®s->r9;
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break;
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case arg_R10:
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rv = ®s->r10;
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break;
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case arg_R11:
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rv = ®s->r11;
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break;
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case arg_R12:
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rv = ®s->r12;
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break;
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case arg_R13:
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rv = ®s->r13;
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break;
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case arg_R14:
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rv = ®s->r14;
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break;
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case arg_R15:
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rv = ®s->r15;
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break;
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#endif
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default:
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printk(KERN_ERR "mmiotrace: Error reg no# %d\n", no);
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}
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return rv;
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}
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unsigned long get_ins_reg_val(unsigned long ins_addr, struct pt_regs *regs)
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{
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unsigned int opcode;
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unsigned char mod_rm;
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int reg;
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unsigned char *p;
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int i, shorted, enlarged, rexr;
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unsigned long rv;
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p = (unsigned char *)ins_addr;
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p += skip_prefix(p, &shorted, &enlarged, &rexr);
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p += get_opcode(p, &opcode);
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for (i = 0; i < ARRAY_SIZE(reg_rop); i++)
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if (reg_rop[i] == opcode) {
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rv = REG_READ;
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goto do_work;
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}
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for (i = 0; i < ARRAY_SIZE(reg_wop); i++)
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if (reg_wop[i] == opcode) {
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rv = REG_WRITE;
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goto do_work;
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}
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printk(KERN_ERR "mmiotrace: Not a register instruction, opcode "
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"0x%02x\n", opcode);
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goto err;
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do_work:
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mod_rm = *p;
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reg = ((mod_rm >> 3) & 0x7) | (rexr << 3);
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switch (get_ins_reg_width(ins_addr)) {
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case 1:
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return *get_reg_w8(reg, regs);
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case 2:
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return *(unsigned short *)get_reg_w32(reg, regs);
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case 4:
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return *(unsigned int *)get_reg_w32(reg, regs);
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#ifdef __amd64__
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case 8:
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return *(unsigned long *)get_reg_w32(reg, regs);
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#endif
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default:
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printk(KERN_ERR "mmiotrace: Error width# %d\n", reg);
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}
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err:
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return 0;
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}
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unsigned long get_ins_imm_val(unsigned long ins_addr)
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{
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unsigned int opcode;
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unsigned char mod_rm;
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unsigned char mod;
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unsigned char *p;
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int i, shorted, enlarged, rexr;
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unsigned long rv;
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p = (unsigned char *)ins_addr;
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p += skip_prefix(p, &shorted, &enlarged, &rexr);
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p += get_opcode(p, &opcode);
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for (i = 0; i < ARRAY_SIZE(imm_wop); i++)
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if (imm_wop[i] == opcode) {
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rv = IMM_WRITE;
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goto do_work;
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}
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printk(KERN_ERR "mmiotrace: Not an immediate instruction, opcode "
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"0x%02x\n", opcode);
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goto err;
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do_work:
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mod_rm = *p;
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mod = mod_rm >> 6;
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p++;
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switch (mod) {
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case 0:
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/* if r/m is 5 we have a 32 disp (IA32 Manual 3, Table 2-2) */
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/* AMD64: XXX Check for address size prefix? */
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if ((mod_rm & 0x7) == 0x5)
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p += 4;
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break;
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case 1:
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p += 1;
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break;
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case 2:
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p += 4;
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break;
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case 3:
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default:
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printk(KERN_ERR "mmiotrace: not a memory access instruction "
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"at 0x%lx, rm_mod=0x%02x\n",
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ins_addr, mod_rm);
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}
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switch (get_ins_reg_width(ins_addr)) {
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case 1:
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return *(unsigned char *)p;
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case 2:
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return *(unsigned short *)p;
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case 4:
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return *(unsigned int *)p;
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#ifdef __amd64__
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case 8:
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return *(unsigned long *)p;
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#endif
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default:
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printk(KERN_ERR "mmiotrace: Error: width.\n");
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}
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err:
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return 0;
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}
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