b37bde1478
This is the driver for latest Blackfin on-chip nand flash controller - use nand_chip and mtd_info common nand driver interface - provide both PIO and dma operation - compiled with ezkit bf548 configuration - use hardware 1-bit ECC - tested with YAFFS2 and can mount YAFFS2 filesystem as rootfs ChangeLog from try#1 - use hweight32() instead of count_bits() - replace bf54x with bf5xx and BF54X with BF5XX - compare against plat->page_size in 2 cases when enable hardware ECC ChangeLog from try#2 - passed nand_test suites - use cpu_relax() instead of busy wait loop - some coding style issue pointed out by Andrew Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: David Woodhouse <dwmw2@infradead.org>
75 lines
1.9 KiB
C
75 lines
1.9 KiB
C
/*
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* file: include/asm-blackfin/mach-bf548/dma.h
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* based on:
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* author:
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*
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* created:
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* description:
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* system mmr register map
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* rev:
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*
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* modified:
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*
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*
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* bugs: enter bugs at http://blackfin.uclinux.org/
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*
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* this program is free software; you can redistribute it and/or modify
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* it under the terms of the gnu general public license as published by
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* the free software foundation; either version 2, or (at your option)
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* any later version.
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*
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* this program is distributed in the hope that it will be useful,
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* but without any warranty; without even the implied warranty of
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* merchantability or fitness for a particular purpose. see the
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* gnu general public license for more details.
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*
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* you should have received a copy of the gnu general public license
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* along with this program; see the file copying.
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* if not, write to the free software foundation,
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* 59 temple place - suite 330, boston, ma 02111-1307, usa.
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*/
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define CH_SPORT0_RX 0
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#define CH_SPORT0_TX 1
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#define CH_SPORT1_RX 2
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#define CH_SPORT1_TX 3
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#define CH_SPI0 4
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#define CH_SPI1 5
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#define CH_UART0_RX 6
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#define CH_UART0_TX 7
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#define CH_UART1_RX 8
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#define CH_UART1_TX 9
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#define CH_ATAPI_RX 10
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#define CH_ATAPI_TX 11
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#define CH_EPPI0 12
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#define CH_EPPI1 13
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#define CH_EPPI2 14
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#define CH_PIXC_IMAGE 15
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#define CH_PIXC_OVERLAY 16
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#define CH_PIXC_OUTPUT 17
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#define CH_SPORT2_RX 18
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#define CH_SPORT2_TX 19
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#define CH_SPORT3_RX 20
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#define CH_SPORT3_TX 21
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#define CH_SDH 22
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#define CH_NFC 22
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#define CH_SPI2 23
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#define CH_MEM_STREAM0_DEST 24
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#define CH_MEM_STREAM0_SRC 25
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#define CH_MEM_STREAM1_DEST 26
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#define CH_MEM_STREAM1_SRC 27
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#define CH_MEM_STREAM2_DEST 28
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#define CH_MEM_STREAM2_SRC 29
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#define CH_MEM_STREAM3_DEST 30
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#define CH_MEM_STREAM3_SRC 31
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#define MAX_BLACKFIN_DMA_CHANNEL 32
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extern int channel2irq(unsigned int channel);
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extern struct dma_register *base_addr[];
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#endif
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