43ae286b7d
In all cases the kaddr is assigned an input register even though it is modified in the assembly code. Let's assign a new variable to the modified value and mark those inline asm with volatile otherwise they get optimized away because the output variable is otherwise not used. Also fix a few conversion errors in copypage-feroceon.c and copypage-v4mc.c. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
/*
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* linux/arch/arm/mm/copypage-xsc3.S
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*
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* Copyright (C) 2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Adapted for 3rd gen XScale core, no more mini-dcache
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* Author: Matt Gilbert (matthew.m.gilbert@intel.com)
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*/
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#include <linux/init.h>
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#include <linux/highmem.h>
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/*
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* General note:
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* We don't really want write-allocate cache behaviour for these functions
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* since that will just eat through 8K of the cache.
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*/
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/*
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* XSC3 optimised copy_user_highpage
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* r0 = destination
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* r1 = source
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*
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* The source page may have some clean entries in the cache already, but we
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* can safely ignore them - break_cow() will flush them out of the cache
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* if we eventually end up using our copied page.
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*
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*/
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static void __attribute__((naked))
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xsc3_mc_copy_user_page(void *kto, const void *kfrom)
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{
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asm("\
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stmfd sp!, {r4, r5, lr} \n\
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mov lr, %0 \n\
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\n\
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pld [r1, #0] \n\
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pld [r1, #32] \n\
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1: pld [r1, #64] \n\
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pld [r1, #96] \n\
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\n\
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2: ldrd r2, [r1], #8 \n\
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mov ip, r0 \n\
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ldrd r4, [r1], #8 \n\
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mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\
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strd r2, [r0], #8 \n\
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ldrd r2, [r1], #8 \n\
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strd r4, [r0], #8 \n\
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ldrd r4, [r1], #8 \n\
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strd r2, [r0], #8 \n\
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strd r4, [r0], #8 \n\
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ldrd r2, [r1], #8 \n\
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mov ip, r0 \n\
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ldrd r4, [r1], #8 \n\
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mcr p15, 0, ip, c7, c6, 1 @ invalidate\n\
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strd r2, [r0], #8 \n\
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ldrd r2, [r1], #8 \n\
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subs lr, lr, #1 \n\
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strd r4, [r0], #8 \n\
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ldrd r4, [r1], #8 \n\
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strd r2, [r0], #8 \n\
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strd r4, [r0], #8 \n\
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bgt 1b \n\
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beq 2b \n\
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\n\
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ldmfd sp!, {r4, r5, pc}"
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:
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: "I" (PAGE_SIZE / 64 - 1));
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}
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void xsc3_mc_copy_user_highpage(struct page *to, struct page *from,
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unsigned long vaddr)
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{
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void *kto, *kfrom;
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kto = kmap_atomic(to, KM_USER0);
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kfrom = kmap_atomic(from, KM_USER1);
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xsc3_mc_copy_user_page(kto, kfrom);
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kunmap_atomic(kfrom, KM_USER1);
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kunmap_atomic(kto, KM_USER0);
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}
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/*
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* XScale optimised clear_user_page
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* r0 = destination
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* r1 = virtual user address of ultimate destination page
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*/
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void xsc3_mc_clear_user_highpage(struct page *page, unsigned long vaddr)
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{
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void *ptr, *kaddr = kmap_atomic(page, KM_USER0);
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asm volatile ("\
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mov r1, %2 \n\
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mov r2, #0 \n\
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mov r3, #0 \n\
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1: mcr p15, 0, %0, c7, c6, 1 @ invalidate line\n\
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strd r2, [%0], #8 \n\
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strd r2, [%0], #8 \n\
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strd r2, [%0], #8 \n\
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strd r2, [%0], #8 \n\
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subs r1, r1, #1 \n\
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bne 1b"
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: "=r" (ptr)
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: "0" (kaddr), "I" (PAGE_SIZE / 32)
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: "r1", "r2", "r3");
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kunmap_atomic(kaddr, KM_USER0);
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}
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struct cpu_user_fns xsc3_mc_user_fns __initdata = {
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.cpu_clear_user_highpage = xsc3_mc_clear_user_highpage,
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.cpu_copy_user_highpage = xsc3_mc_copy_user_highpage,
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};
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