e344b63eee
The attached patches provides part 7 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/*
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* Xtensa Special Register symbolic names
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*/
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/* $Id: specreg.h,v 1.2 2003/03/07 19:15:18 joetaylor Exp $ */
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/*
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* Copyright (c) 2003 Tensilica, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2.1 of the GNU Lesser General Public
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* License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Further, this software is distributed without any warranty that it is
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* free of the rightful claim of any third person regarding infringement
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* or the like. Any license provided herein, whether implied or
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* otherwise, applies only to this software file. Patent licenses, if
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* any, provided herein do not apply to combinations of this program with
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* other software, or any other product whatsoever.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, write the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
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* USA.
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*/
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#ifndef XTENSA_SPECREG_H
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#define XTENSA_SPECREG_H
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/* Include these special register bitfield definitions, for historical reasons: */
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#include <xtensa/corebits.h>
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/* Special registers: */
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#define LBEG 0
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#define LEND 1
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#define LCOUNT 2
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#define SAR 3
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#define WINDOWBASE 72
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#define WINDOWSTART 73
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#define PTEVADDR 83
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#define RASID 90
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#define ITLBCFG 91
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#define DTLBCFG 92
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#define IBREAKENABLE 96
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#define DDR 104
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#define IBREAKA_0 128
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#define IBREAKA_1 129
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#define DBREAKA_0 144
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#define DBREAKA_1 145
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#define DBREAKC_0 160
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#define DBREAKC_1 161
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#define EPC_1 177
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#define EPC_2 178
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#define EPC_3 179
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#define EPC_4 180
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#define DEPC 192
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#define EPS_2 194
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#define EPS_3 195
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#define EPS_4 196
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#define EXCSAVE_1 209
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#define EXCSAVE_2 210
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#define EXCSAVE_3 211
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#define EXCSAVE_4 212
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#define INTERRUPT 226
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#define INTENABLE 228
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#define PS 230
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#define EXCCAUSE 232
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#define DEBUGCAUSE 233
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#define CCOUNT 234
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#define ICOUNT 236
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#define ICOUNTLEVEL 237
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#define EXCVADDR 238
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#define CCOMPARE_0 240
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#define CCOMPARE_1 241
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#define CCOMPARE_2 242
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#define MISC_REG_0 244
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#define MISC_REG_1 245
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/* Special cases (bases of special register series): */
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#define IBREAKA 128
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#define DBREAKA 144
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#define DBREAKC 160
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#define EPC 176
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#define EPS 192
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#define EXCSAVE 208
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#define CCOMPARE 240
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/* Special names for read-only and write-only interrupt registers: */
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#define INTREAD 226
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#define INTSET 226
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#define INTCLEAR 227
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#endif /* XTENSA_SPECREG_H */
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