2296fb7ff0
Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
133 lines
4.6 KiB
C
133 lines
4.6 KiB
C
/*
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* File: include/asm-blackfin/cplb.h
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* Based on: include/asm-blackfin/mach-bf537/bf537.h
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* Author: Robin Getz <rgetz@blackfin.uclinux.org>
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*
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* Created: 2000
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* Description: Common CPLB definitions for CPLB init
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*
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* Modified:
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* Copyright 2004-2007 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef _CPLB_H
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#define _CPLB_H
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#include <asm/blackfin.h>
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#include <asm/mach/anomaly.h>
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#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
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#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
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#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
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#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
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/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
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#if ANOMALY_05000158
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#define ANOMALY_05000158_WORKAROUND 0x200
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#else
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#define ANOMALY_05000158_WORKAROUND 0x0
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#endif
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#define CPLB_COMMON (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
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#ifdef CONFIG_BFIN_WB /*Write Back Policy */
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_COMMON)
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#else /*Write Through */
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#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_COMMON)
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#endif
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#define L1_DMEMORY (CPLB_LOCK | CPLB_COMMON)
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#define L2_MEMORY (CPLB_COMMON)
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#define SDRAM_DNON_CHBL (CPLB_COMMON)
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#define SDRAM_EBIU (CPLB_COMMON)
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#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
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#define SIZE_1K 0x00000400 /* 1K */
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#define SIZE_4K 0x00001000 /* 4K */
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#define SIZE_1M 0x00100000 /* 1M */
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#define SIZE_4M 0x00400000 /* 4M */
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#define MAX_CPLBS (16 * 2)
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#define ASYNC_MEMORY_CPLB_COVERAGE ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
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ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
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/*
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* Number of required data CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 16 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Data Memory
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* possibly 1 for L2 Data Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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* 1 for ASYNC Memory
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*/
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#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 \
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+ ASYNC_MEMORY_CPLB_COVERAGE) * 2)
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/*
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* Number of required instruction CPLB switchtable entries
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* MEMSIZE / 4 (we mostly install 4M page size CPLBs
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* approx 12 for smaller 1MB page size CPLBs for allignment purposes
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* 1 for L1 Instruction Memory
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* possibly 1 for L2 Instruction Memory
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* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
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*/
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#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
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#define CPLB_ENABLE_ICACHE_P 0
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#define CPLB_ENABLE_DCACHE_P 1
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#define CPLB_ENABLE_DCACHE2_P 2
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#define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
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#define CPLB_ENABLE_ICPLBS_P 4
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#define CPLB_ENABLE_DCPLBS_P 5
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#define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
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#define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
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#define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
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#define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
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#define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
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#define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
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#define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
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CPLB_ENABLE_ICPLBS | \
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CPLB_ENABLE_DCPLBS
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#define CPLB_RELOADED 0x0000
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#define CPLB_NO_UNLOCKED 0x0001
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#define CPLB_NO_ADDR_MATCH 0x0002
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#define CPLB_PROT_VIOL 0x0003
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#define CPLB_UNKNOWN_ERR 0x0004
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#define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
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#define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
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#define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
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#define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
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#define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
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#define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
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#define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
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#define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
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#endif /* _CPLB_H */
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