5bc6e3cfe6
The Blackfin SMP port was missing CPLB entries for Core B on-chip L1 SRAM regions. Any code that attempted to use these would wrongly crash due to a CPLB miss. Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org> |
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.. | ||
cplb-mpu | ||
cplb-nompu | ||
.gitignore | ||
asm-offsets.c | ||
bfin_dma_5xx.c | ||
bfin_gpio.c | ||
bfin_ksyms.c | ||
cplbinfo.c | ||
dma-mapping.c | ||
early_printk.c | ||
entry.S | ||
fixed_code.S | ||
flat.c | ||
ftrace-entry.S | ||
ftrace.c | ||
gptimers.c | ||
init_task.c | ||
ipipe.c | ||
irqchip.c | ||
kgdb_test.c | ||
kgdb.c | ||
Makefile | ||
module.c | ||
process.c | ||
ptrace.c | ||
reboot.c | ||
setup.c | ||
signal.c | ||
stacktrace.c | ||
sys_bfin.c | ||
time-ts.c | ||
time.c | ||
traps.c | ||
vmlinux.lds.S |