b6884a17fc
This changesets syncs the OpenSource driver for DiBcom demodulators with version 2.1.3 of DiBcom reference driver. There were some improvements since the last release for linux-dvb, e.g.: - stepped AGC startup - less space for initialization - diversity synchronization Furthermore this changeset contains the following things: - latest AGC settings for MT2266-based devices (namely Nova-TD and other) will improve the sensitivity - support for STK7700D reference design in dib0700-devices - remove some line-breaks when debugging is enabled - getting rid of layer between frontend_parameters and ofdm_channel used in dib*-drivers Signed-off-by: Patrick Boettcher <pboettcher@dibcom.fr> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
289 lines
7.5 KiB
C
289 lines
7.5 KiB
C
/*
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* Driver for Microtune MT2266 "Direct conversion low power broadband tuner"
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*
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* Copyright (c) 2007 Olivier DANET <odanet@caramail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/delay.h>
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#include <linux/dvb/frontend.h>
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#include <linux/i2c.h>
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#include "dvb_frontend.h"
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#include "mt2266.h"
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#define I2C_ADDRESS 0x60
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#define REG_PART_REV 0
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#define REG_TUNE 1
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#define REG_BAND 6
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#define REG_BANDWIDTH 8
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#define REG_LOCK 0x12
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#define PART_REV 0x85
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struct mt2266_priv {
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struct mt2266_config *cfg;
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struct i2c_adapter *i2c;
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u32 frequency;
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u32 bandwidth;
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};
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/* Here, frequencies are expressed in kiloHertz to avoid 32 bits overflows */
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static int debug;
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module_param(debug, int, 0644);
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MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
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#define dprintk(args...) do { if (debug) {printk(KERN_DEBUG "MT2266: " args); printk("\n"); }} while (0)
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// Reads a single register
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static int mt2266_readreg(struct mt2266_priv *priv, u8 reg, u8 *val)
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{
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struct i2c_msg msg[2] = {
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{ .addr = priv->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
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{ .addr = priv->cfg->i2c_address, .flags = I2C_M_RD, .buf = val, .len = 1 },
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};
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if (i2c_transfer(priv->i2c, msg, 2) != 2) {
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printk(KERN_WARNING "MT2266 I2C read failed\n");
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return -EREMOTEIO;
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}
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return 0;
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}
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// Writes a single register
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static int mt2266_writereg(struct mt2266_priv *priv, u8 reg, u8 val)
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{
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u8 buf[2] = { reg, val };
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struct i2c_msg msg = {
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.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = 2
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};
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if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
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printk(KERN_WARNING "MT2266 I2C write failed\n");
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return -EREMOTEIO;
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}
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return 0;
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}
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// Writes a set of consecutive registers
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static int mt2266_writeregs(struct mt2266_priv *priv,u8 *buf, u8 len)
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{
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struct i2c_msg msg = {
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.addr = priv->cfg->i2c_address, .flags = 0, .buf = buf, .len = len
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};
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if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
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printk(KERN_WARNING "MT2266 I2C write failed (len=%i)\n",(int)len);
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return -EREMOTEIO;
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}
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return 0;
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}
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// Initialisation sequences
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static u8 mt2266_init1[] = {
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REG_TUNE,
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0x00, 0x00, 0x28, 0x00, 0x52, 0x99, 0x3f };
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static u8 mt2266_init2[] = {
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0x17, 0x6d, 0x71, 0x61, 0xc0, 0xbf, 0xff, 0xdc, 0x00, 0x0a,
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0xd4, 0x03, 0x64, 0x64, 0x64, 0x64, 0x22, 0xaa, 0xf2, 0x1e, 0x80, 0x14, 0x01, 0x01, 0x01, 0x01,
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0x01, 0x01, 0x7f, 0x5e, 0x3f, 0xff, 0xff, 0xff, 0x00, 0x77, 0x0f, 0x2d };
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static u8 mt2266_init_8mhz[] = {
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REG_BANDWIDTH,
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0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22 };
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static u8 mt2266_init_7mhz[] = {
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REG_BANDWIDTH,
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0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32 };
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static u8 mt2266_init_6mhz[] = {
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REG_BANDWIDTH,
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0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7, 0xa7 };
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#define FREF 30000 // Quartz oscillator 30 MHz
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static int mt2266_set_params(struct dvb_frontend *fe, struct dvb_frontend_parameters *params)
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{
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struct mt2266_priv *priv;
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int ret=0;
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u32 freq;
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u32 tune;
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u8 lnaband;
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u8 b[10];
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int i;
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priv = fe->tuner_priv;
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mt2266_writereg(priv,0x17,0x6d);
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mt2266_writereg(priv,0x1c,0xff);
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freq = params->frequency / 1000; // Hz -> kHz
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priv->bandwidth = (fe->ops.info.type == FE_OFDM) ? params->u.ofdm.bandwidth : 0;
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priv->frequency = freq * 1000;
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tune=2 * freq * (8192/16) / (FREF/16);
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if (freq <= 495000) lnaband = 0xEE; else
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if (freq <= 525000) lnaband = 0xDD; else
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if (freq <= 550000) lnaband = 0xCC; else
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if (freq <= 580000) lnaband = 0xBB; else
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if (freq <= 605000) lnaband = 0xAA; else
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if (freq <= 630000) lnaband = 0x99; else
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if (freq <= 655000) lnaband = 0x88; else
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if (freq <= 685000) lnaband = 0x77; else
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if (freq <= 710000) lnaband = 0x66; else
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if (freq <= 735000) lnaband = 0x55; else
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if (freq <= 765000) lnaband = 0x44; else
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if (freq <= 802000) lnaband = 0x33; else
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if (freq <= 840000) lnaband = 0x22; else lnaband = 0x11;
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msleep(100);
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mt2266_writeregs(priv,(params->u.ofdm.bandwidth==BANDWIDTH_6_MHZ)?mt2266_init_6mhz:
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(params->u.ofdm.bandwidth==BANDWIDTH_7_MHZ)?mt2266_init_7mhz:
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mt2266_init_8mhz,sizeof(mt2266_init_8mhz));
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b[0] = REG_TUNE;
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b[1] = (tune >> 8) & 0x1F;
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b[2] = tune & 0xFF;
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b[3] = tune >> 13;
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mt2266_writeregs(priv,b,4);
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dprintk("set_parms: tune=%d band=%d",(int)tune,(int)lnaband);
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dprintk("set_parms: [1..3]: %2x %2x %2x",(int)b[1],(int)b[2],(int)b[3]);
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b[0] = 0x05;
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b[1] = 0x62;
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b[2] = lnaband;
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mt2266_writeregs(priv,b,3);
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//Waits for pll lock or timeout
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i = 0;
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do {
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mt2266_readreg(priv,REG_LOCK,b);
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if ((b[0] & 0x40)==0x40)
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break;
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msleep(10);
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i++;
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} while (i<10);
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dprintk("Lock when i=%i",(int)i);
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return ret;
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}
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static void mt2266_calibrate(struct mt2266_priv *priv)
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{
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mt2266_writereg(priv,0x11,0x03);
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mt2266_writereg(priv,0x11,0x01);
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mt2266_writeregs(priv,mt2266_init1,sizeof(mt2266_init1));
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mt2266_writeregs(priv,mt2266_init2,sizeof(mt2266_init2));
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mt2266_writereg(priv,0x33,0x5e);
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mt2266_writereg(priv,0x10,0x10);
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mt2266_writereg(priv,0x10,0x00);
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mt2266_writeregs(priv,mt2266_init_8mhz,sizeof(mt2266_init_8mhz));
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msleep(25);
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mt2266_writereg(priv,0x17,0x6d);
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mt2266_writereg(priv,0x1c,0x00);
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msleep(75);
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mt2266_writereg(priv,0x17,0x6d);
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mt2266_writereg(priv,0x1c,0xff);
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}
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static int mt2266_get_frequency(struct dvb_frontend *fe, u32 *frequency)
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{
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struct mt2266_priv *priv = fe->tuner_priv;
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*frequency = priv->frequency;
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return 0;
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}
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static int mt2266_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
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{
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struct mt2266_priv *priv = fe->tuner_priv;
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*bandwidth = priv->bandwidth;
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return 0;
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}
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static int mt2266_init(struct dvb_frontend *fe)
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{
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struct mt2266_priv *priv = fe->tuner_priv;
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mt2266_writereg(priv,0x17,0x6d);
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mt2266_writereg(priv,0x1c,0xff);
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return 0;
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}
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static int mt2266_sleep(struct dvb_frontend *fe)
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{
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struct mt2266_priv *priv = fe->tuner_priv;
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mt2266_writereg(priv,0x17,0x6d);
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mt2266_writereg(priv,0x1c,0x00);
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return 0;
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}
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static int mt2266_release(struct dvb_frontend *fe)
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{
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kfree(fe->tuner_priv);
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fe->tuner_priv = NULL;
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return 0;
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}
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static const struct dvb_tuner_ops mt2266_tuner_ops = {
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.info = {
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.name = "Microtune MT2266",
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.frequency_min = 470000000,
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.frequency_max = 860000000,
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.frequency_step = 50000,
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},
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.release = mt2266_release,
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.init = mt2266_init,
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.sleep = mt2266_sleep,
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.set_params = mt2266_set_params,
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.get_frequency = mt2266_get_frequency,
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.get_bandwidth = mt2266_get_bandwidth
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};
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struct dvb_frontend * mt2266_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mt2266_config *cfg)
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{
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struct mt2266_priv *priv = NULL;
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u8 id = 0;
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priv = kzalloc(sizeof(struct mt2266_priv), GFP_KERNEL);
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if (priv == NULL)
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return NULL;
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priv->cfg = cfg;
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priv->i2c = i2c;
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if (mt2266_readreg(priv,0,&id) != 0) {
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kfree(priv);
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return NULL;
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}
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if (id != PART_REV) {
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kfree(priv);
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return NULL;
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}
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printk(KERN_INFO "MT2266: successfully identified\n");
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memcpy(&fe->ops.tuner_ops, &mt2266_tuner_ops, sizeof(struct dvb_tuner_ops));
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fe->tuner_priv = priv;
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mt2266_calibrate(priv);
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return fe;
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}
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EXPORT_SYMBOL(mt2266_attach);
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MODULE_AUTHOR("Olivier DANET");
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MODULE_DESCRIPTION("Microtune MT2266 silicon tuner driver");
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MODULE_LICENSE("GPL");
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