2874c5fd28
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
56 lines
1.3 KiB
C
56 lines
1.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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*
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* Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2011 Wind River Systems,
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* written by Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/bug.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/memblock.h>
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/of_address.h>
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#include <asm/cpu-info.h>
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unsigned long PCIBIOS_MIN_IO;
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EXPORT_SYMBOL(PCIBIOS_MIN_IO);
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unsigned long PCIBIOS_MIN_MEM;
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EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
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static int __init pcibios_set_cache_line_size(void)
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{
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unsigned int lsize;
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/*
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* Set PCI cacheline size to that of the highest level in the
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* cache hierarchy.
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*/
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lsize = cpu_dcache_line_size();
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lsize = cpu_scache_line_size() ? : lsize;
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lsize = cpu_tcache_line_size() ? : lsize;
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BUG_ON(!lsize);
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pci_dfl_cache_line_size = lsize >> 2;
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pr_debug("PCI: pci_cache_line_size set to %d bytes\n", lsize);
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return 0;
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}
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arch_initcall(pcibios_set_cache_line_size);
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void pci_resource_to_user(const struct pci_dev *dev, int bar,
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const struct resource *rsrc, resource_size_t *start,
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resource_size_t *end)
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{
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phys_addr_t size = resource_size(rsrc);
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*start = fixup_bigphys_addr(rsrc->start, size);
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*end = rsrc->start + size - 1;
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}
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