3863c74b51
MPU power domain bank 0 bits are displayed in position of bank 1 in PWRSTS and PREPWRSTS registers. So read them from correct position Signed-off-by: Thara Gopinath <thara@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
188 lines
5.5 KiB
C
188 lines
5.5 KiB
C
/*
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* OMAP2/3 powerdomain control
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*
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* Copyright (C) 2007-8 Texas Instruments, Inc.
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* Copyright (C) 2007-8 Nokia Corporation
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*
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* Written by Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN
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#define ASM_ARM_ARCH_OMAP_POWERDOMAIN
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#include <linux/types.h>
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#include <linux/list.h>
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#include <asm/atomic.h>
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#include <plat/cpu.h>
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/* Powerdomain basic power states */
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#define PWRDM_POWER_OFF 0x0
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#define PWRDM_POWER_RET 0x1
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#define PWRDM_POWER_INACTIVE 0x2
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#define PWRDM_POWER_ON 0x3
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#define PWRDM_MAX_PWRSTS 4
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/* Powerdomain allowable state bitfields */
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#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \
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(1 << PWRDM_POWER_ON))
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#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \
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(1 << PWRDM_POWER_RET))
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#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
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/* Powerdomain flags */
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#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
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#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
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* in MEM bank 1 position. This is
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* true for OMAP3430
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*/
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/*
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* Number of memory banks that are power-controllable. On OMAP3430, the
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* maximum is 4.
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*/
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#define PWRDM_MAX_MEM_BANKS 4
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/*
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* Maximum number of clockdomains that can be associated with a powerdomain.
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* CORE powerdomain on OMAP3 is the worst case
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*/
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#define PWRDM_MAX_CLKDMS 4
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/* XXX A completely arbitrary number. What is reasonable here? */
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#define PWRDM_TRANSITION_BAILOUT 100000
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struct clockdomain;
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struct powerdomain;
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/* Encodes dependencies between powerdomains - statically defined */
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struct pwrdm_dep {
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/* Powerdomain name */
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const char *pwrdm_name;
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/* Powerdomain pointer - resolved by the powerdomain code */
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struct powerdomain *pwrdm;
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/* Flags to mark OMAP chip restrictions, etc. */
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const struct omap_chip_id omap_chip;
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};
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struct powerdomain {
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/* Powerdomain name */
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const char *name;
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/* the address offset from CM_BASE/PRM_BASE */
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const s16 prcm_offs;
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/* Used to represent the OMAP chip types containing this pwrdm */
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const struct omap_chip_id omap_chip;
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/* Powerdomains that can be told to wake this powerdomain up */
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struct pwrdm_dep *wkdep_srcs;
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/* Powerdomains that can be told to keep this pwrdm from inactivity */
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struct pwrdm_dep *sleepdep_srcs;
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/* Bit shift of this powerdomain's PM_WKDEP/CM_SLEEPDEP bit */
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const u8 dep_bit;
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/* Possible powerdomain power states */
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const u8 pwrsts;
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/* Possible logic power states when pwrdm in RETENTION */
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const u8 pwrsts_logic_ret;
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/* Powerdomain flags */
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const u8 flags;
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/* Number of software-controllable memory banks in this powerdomain */
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const u8 banks;
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/* Possible memory bank pwrstates when pwrdm in RETENTION */
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const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
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/* Possible memory bank pwrstates when pwrdm is ON */
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const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
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/* Clockdomains in this powerdomain */
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struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
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struct list_head node;
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int state;
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unsigned state_counter[PWRDM_MAX_PWRSTS];
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#ifdef CONFIG_PM_DEBUG
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s64 timer;
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s64 state_timer[PWRDM_MAX_PWRSTS];
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#endif
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};
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void pwrdm_init(struct powerdomain **pwrdm_list);
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int pwrdm_register(struct powerdomain *pwrdm);
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int pwrdm_unregister(struct powerdomain *pwrdm);
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struct powerdomain *pwrdm_lookup(const char *name);
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int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
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void *user);
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int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
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void *user);
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int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
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int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
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int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
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int (*fn)(struct powerdomain *pwrdm,
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struct clockdomain *clkdm));
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int pwrdm_add_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
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int pwrdm_del_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
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int pwrdm_read_wkdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
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int pwrdm_add_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
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int pwrdm_del_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
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int pwrdm_read_sleepdep(struct powerdomain *pwrdm1, struct powerdomain *pwrdm2);
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int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
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int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
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int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
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int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
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int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
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int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
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int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
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int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
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int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
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int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
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int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
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bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
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int pwrdm_wait_transition(struct powerdomain *pwrdm);
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int pwrdm_state_switch(struct powerdomain *pwrdm);
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int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
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int pwrdm_pre_transition(void);
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int pwrdm_post_transition(void);
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#endif
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