1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
323 lines
9.8 KiB
C
323 lines
9.8 KiB
C
/*
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* include/asm-ppc/gt64260.h
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*
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* Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines.
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ASMPPC_GT64260_H
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#define __ASMPPC_GT64260_H
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/slab.h>
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#include <asm/byteorder.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/machdep.h>
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#include <asm/pci-bridge.h>
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#include <asm/gt64260_defs.h>
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extern u32 gt64260_base;
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extern u32 gt64260_irq_base; /* We handle the next 96 IRQs from here */
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extern u32 gt64260_revision;
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extern u8 gt64260_pci_exclude_bridge;
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#ifndef TRUE
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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/* IRQs defined by the 64260 */
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#define GT64260_IRQ_MPSC0 40
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#define GT64260_IRQ_MPSC1 42
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#define GT64260_IRQ_SDMA 36
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/*
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* Define a default physical memory map to be set up on the bridge.
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* Also define a struct to pass that info from board-specific routines to
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* GT64260 generic set up routines. By passing this info in, the board
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* support developer can modify it at will.
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*/
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/*
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* This is the default memory map:
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* CPU PCI
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* --- ---
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* PCI 0 I/O: 0xfa000000-0xfaffffff 0x00000000-0x00ffffff
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* PCI 1 I/O: 0xfb000000-0xfbffffff 0x01000000-0x01ffffff
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* PCI 0 MEM: 0x80000000-0x8fffffff 0x80000000-0x8fffffff
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* PCI 1 MEM: 0x90000000-0x9fffffff 0x90000000-0x9fffffff
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*/
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/* Default physical memory map for the GT64260 bridge */
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/*
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* PCI Bus 0 Definitions
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*/
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#define GT64260_PCI_0_IO_SIZE 0x01000000U
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#define GT64260_PCI_0_MEM_SIZE 0x10000000U
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/* Processor Physical addresses */
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#define GT64260_PCI_0_IO_START_PROC 0xfa000000U
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#define GT64260_PCI_0_IO_END_PROC (GT64260_PCI_0_IO_START_PROC + \
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GT64260_PCI_0_IO_SIZE - 1)
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/* PCI 0 addresses */
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#define GT64260_PCI_0_IO_START 0x00000000U
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#define GT64260_PCI_0_IO_END (GT64260_PCI_0_IO_START + \
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GT64260_PCI_0_IO_SIZE - 1)
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/* Processor Physical addresses */
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#define GT64260_PCI_0_MEM_START_PROC 0x80000000U
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#define GT64260_PCI_0_MEM_END_PROC (GT64260_PCI_0_MEM_START_PROC + \
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GT64260_PCI_0_MEM_SIZE - 1)
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/* PCI 0 addresses */
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#define GT64260_PCI_0_MEM_START 0x80000000U
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#define GT64260_PCI_0_MEM_END (GT64260_PCI_0_MEM_START + \
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GT64260_PCI_0_MEM_SIZE - 1)
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/*
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* PCI Bus 1 Definitions
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*/
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#define GT64260_PCI_1_IO_SIZE 0x01000000U
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#define GT64260_PCI_1_MEM_SIZE 0x10000000U
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/* PCI 1 addresses */
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#define GT64260_PCI_1_IO_START 0x01000000U
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#define GT64260_PCI_1_IO_END (GT64260_PCI_1_IO_START + \
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GT64260_PCI_1_IO_SIZE - 1)
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/* Processor Physical addresses */
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#define GT64260_PCI_1_IO_START_PROC 0xfb000000U
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#define GT64260_PCI_1_IO_END_PROC (GT64260_PCI_1_IO_START_PROC + \
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GT64260_PCI_1_IO_SIZE - 1)
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/* PCI 1 addresses */
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#define GT64260_PCI_1_MEM_START 0x90000000U
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#define GT64260_PCI_1_MEM_END (GT64260_PCI_1_MEM_START + \
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GT64260_PCI_1_MEM_SIZE - 1)
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/* Processor Physical addresses */
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#define GT64260_PCI_1_MEM_START_PROC 0x90000000U
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#define GT64260_PCI_1_MEM_END_PROC (GT64260_PCI_1_MEM_START_PROC + \
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GT64260_PCI_1_MEM_SIZE - 1)
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/* Define struct to pass mem-map info into gt64260_common.c code */
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typedef struct {
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struct pci_controller *hose_a;
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struct pci_controller *hose_b;
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u32 mem_size;
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u32 pci_0_io_start_proc;
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u32 pci_0_io_start_pci;
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u32 pci_0_io_size;
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u32 pci_0_io_swap;
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u32 pci_0_mem_start_proc;
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u32 pci_0_mem_start_pci_hi;
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u32 pci_0_mem_start_pci_lo;
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u32 pci_0_mem_size;
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u32 pci_0_mem_swap;
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u32 pci_1_io_start_proc;
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u32 pci_1_io_start_pci;
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u32 pci_1_io_size;
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u32 pci_1_io_swap;
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u32 pci_1_mem_start_proc;
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u32 pci_1_mem_start_pci_hi;
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u32 pci_1_mem_start_pci_lo;
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u32 pci_1_mem_size;
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u32 pci_1_mem_swap;
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} gt64260_bridge_info_t;
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#define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) { \
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(ip)->mem_size = (ms); \
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\
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(ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC; \
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(ip)->pci_0_io_start_pci = GT64260_PCI_0_IO_START; \
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(ip)->pci_0_io_size = GT64260_PCI_0_IO_SIZE; \
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(ip)->pci_0_io_swap = GT64260_CPU_PCI_SWAP_NONE; \
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\
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(ip)->pci_0_mem_start_proc = GT64260_PCI_0_MEM_START_PROC; \
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(ip)->pci_0_mem_start_pci_hi = 0x00000000; \
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(ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START; \
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(ip)->pci_0_mem_size = GT64260_PCI_0_MEM_SIZE; \
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(ip)->pci_0_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \
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\
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(ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC; \
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(ip)->pci_1_io_start_pci = GT64260_PCI_1_IO_START; \
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(ip)->pci_1_io_size = GT64260_PCI_1_IO_SIZE; \
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(ip)->pci_1_io_swap = GT64260_CPU_PCI_SWAP_NONE; \
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\
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(ip)->pci_1_mem_start_proc = GT64260_PCI_1_MEM_START_PROC; \
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(ip)->pci_1_mem_start_pci_hi = 0x00000000; \
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(ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START; \
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(ip)->pci_1_mem_size = GT64260_PCI_1_MEM_SIZE; \
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(ip)->pci_1_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \
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}
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/*
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*****************************************************************************
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*
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* I/O macros to access the 64260's registers
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*
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*****************************************************************************
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*/
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extern inline uint32_t gt_read(uint32_t offs){
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return (in_le32((volatile uint *)(gt64260_base + offs)));
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}
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extern inline void gt_write(uint32_t offs, uint32_t d){
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out_le32((volatile uint *)(gt64260_base + offs), d);
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}
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#if 0 /* paranoid SMP version */
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extern inline void gt_modify(u32 offs, u32 data, u32 mask) \
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{
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uint32_t reg;
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spin_lock(>64260_lock);
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reg = gt_read(offs) & (~mask); /* zero any bits we care about*/
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reg |= data & mask; /* set bits from the data */
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gt_write(offs, reg);
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spin_unlock(>64260_lock);
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}
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#else
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extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask)
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{
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uint32_t reg;
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reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/
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reg |= (data) & (mask); /* set bits from the data */
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gt_write(offs, reg);
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}
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#endif
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#define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits)
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#define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits)
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/*
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*****************************************************************************
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*
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* Function Prototypes
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*
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*****************************************************************************
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*/
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int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info,
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int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)));
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int gt64260_bridge_init(gt64260_bridge_info_t *info);
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int gt64260_cpu_scs_set_window(u32 window,
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u32 base_addr,
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u32 size);
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int gt64260_cpu_cs_set_window(u32 window,
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u32 base_addr,
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u32 size);
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int gt64260_cpu_boot_set_window(u32 base_addr,
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u32 size);
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int gt64260_cpu_set_pci_io_window(u32 pci_bus,
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u32 cpu_base_addr,
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u32 pci_base_addr,
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u32 size,
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u32 swap);
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int gt64260_cpu_set_pci_mem_window(u32 pci_bus,
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u32 window,
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u32 cpu_base_addr,
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u32 pci_base_addr_hi,
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u32 pci_base_addr_lo,
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u32 size,
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u32 swap_64bit);
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int gt64260_cpu_prot_set_window(u32 window,
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u32 base_addr,
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u32 size,
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u32 access_bits);
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int gt64260_cpu_snoop_set_window(u32 window,
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u32 base_addr,
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u32 size,
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u32 snoop_type);
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void gt64260_cpu_disable_all_windows(void);
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int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits);
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int gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
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u32 window,
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u32 pci_base_addr,
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u32 cpu_base_addr,
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u32 size);
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int gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
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u32 window,
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u32 pci_base_addr,
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u32 cpu_base_addr,
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u32 size);
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int gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
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u32 pci_base_addr,
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u32 cpu_base_addr,
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u32 size);
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int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
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u32 window,
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u32 pci_base_addr,
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u32 other_bus_base_addr,
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u32 size);
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int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
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u32 pci_base_addr,
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u32 other_bus_base_addr,
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u32 size);
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int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
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u32 window,
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u32 pci_base_addr_hi,
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u32 pci_base_addr_lo,
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u32 cpu_base_addr,
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u32 size);
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int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
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u32 window,
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u32 pci_base_addr_hi,
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u32 pci_base_addr_lo,
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u32 cpu_base_addr,
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u32 size);
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int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
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u32 pci_base_addr_hi,
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u32 pci_base_addr_lo,
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u32 cpu_base_addr,
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u32 size);
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int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
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u32 window,
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u32 pci_base_addr_hi,
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u32 pci_base_addr_lo,
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u32 other_bus_base_addr,
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u32 size);
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int gt64260_pci_acc_cntl_set_window(u32 pci_bus,
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u32 window,
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u32 base_addr_hi,
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u32 base_addr_lo,
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u32 size,
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u32 features);
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int gt64260_pci_snoop_set_window(u32 pci_bus,
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u32 window,
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u32 base_addr_hi,
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u32 base_addr_lo,
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u32 size,
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u32 snoop_type);
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int gt64260_set_base(u32 new_base);
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int gt64260_get_base(u32 *base);
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int gt64260_pci_exclude_device(u8 bus, u8 devfn);
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void gt64260_init_irq(void);
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int gt64260_get_irq(struct pt_regs *regs);
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void gt64260_mpsc_progress(char *s, unsigned short hex);
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#endif /* __ASMPPC_GT64260_H */
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