4b8bca7028
The I2C and UARTS are clocked by the I/O clock, use its rate for these devices. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1670/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
138 lines
3.6 KiB
C
138 lines
3.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004-2007 Cavium Networks
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*/
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#include <linux/console.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_reg.h>
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#include <linux/tty.h>
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#include <linux/irq.h>
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#include <asm/time.h>
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#include <asm/octeon/octeon.h>
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#define DEBUG_UART 1
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unsigned int octeon_serial_in(struct uart_port *up, int offset)
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{
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int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
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if (offset == UART_IIR && (rv & 0xf) == 7) {
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/* Busy interrupt, read the USR (39) and try again. */
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cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
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rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
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}
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return rv;
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}
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void octeon_serial_out(struct uart_port *up, int offset, int value)
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{
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/*
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* If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
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* working.
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*/
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if (offset == UART_LCR)
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value &= 0x9f;
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cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
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}
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/*
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* Allocated in .bss, so it is all zeroed.
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*/
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#define OCTEON_MAX_UARTS 3
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static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1];
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static struct platform_device octeon_uart8250_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = octeon_uart8250_data,
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},
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};
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static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
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{
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p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
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p->type = PORT_OCTEON;
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p->iotype = UPIO_MEM;
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p->regshift = 3; /* I/O addresses are every 8 bytes */
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if (octeon_is_simulation())
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/* Make simulator output fast*/
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p->uartclk = 115200 * 16;
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else
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p->uartclk = octeon_get_io_clock_rate();
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p->serial_in = octeon_serial_in;
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p->serial_out = octeon_serial_out;
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}
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static int __init octeon_serial_init(void)
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{
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int enable_uart0;
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int enable_uart1;
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int enable_uart2;
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struct plat_serial8250_port *p;
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#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
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/*
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* If we are configured to run as the second of two kernels,
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* disable uart0 and enable uart1. Uart0 is owned by the first
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* kernel
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*/
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enable_uart0 = 0;
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enable_uart1 = 1;
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#else
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/*
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* We are configured for the first kernel. We'll enable uart0
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* if the bootloader told us to use 0, otherwise will enable
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* uart 1.
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*/
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enable_uart0 = (octeon_get_boot_uart() == 0);
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enable_uart1 = (octeon_get_boot_uart() == 1);
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#ifdef CONFIG_KGDB
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enable_uart1 = 1;
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#endif
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#endif
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/* Right now CN52XX is the only chip with a third uart */
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enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX);
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p = octeon_uart8250_data;
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if (enable_uart0) {
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/* Add a ttyS device for hardware uart 0 */
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octeon_uart_set_common(p);
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p->membase = (void *) CVMX_MIO_UARTX_RBR(0);
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p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1);
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p->irq = OCTEON_IRQ_UART0;
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p++;
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}
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if (enable_uart1) {
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/* Add a ttyS device for hardware uart 1 */
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octeon_uart_set_common(p);
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p->membase = (void *) CVMX_MIO_UARTX_RBR(1);
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p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1);
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p->irq = OCTEON_IRQ_UART1;
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p++;
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}
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if (enable_uart2) {
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/* Add a ttyS device for hardware uart 2 */
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octeon_uart_set_common(p);
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p->membase = (void *) CVMX_MIO_UART2_RBR;
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p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1);
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p->irq = OCTEON_IRQ_UART2;
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p++;
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}
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BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]);
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return platform_device_register(&octeon_uart8250_device);
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}
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device_initcall(octeon_serial_init);
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