284d115ec9
The PXA25x and PXA27x USB device controller register definitions are different. Currently, they live side by side in pxa-regs.h, but only one set is available depending on the setting of PXA25x or PXA27x. This means that if we build to support both PXA25x and PXA27x, the PXA27x definitions are unavailable, even to PXA27x specific code. Remove these definitions from pxa-regs.h, and place them in separate files. Include these files where appropriate. Note: according to the dependencies in drivers/usb/gadget/Kconfig, we do not support the UDC on PXA27x nor PXA3xx CPUs, so remove the platform devices from pxa27x.c and pxa3xx.c. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
578 lines
13 KiB
C
578 lines
13 KiB
C
/*
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* linux/arch/arm/mach-pxa/pxa3xx.c
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*
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* code specific to pxa3xx aka Monahans
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*
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* Copyright (C) 2006 Marvell International Ltd.
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*
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* 2007-09-02: eric miao <eric.miao@marvell.com>
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* initial version
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/sysdev.h>
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#include <asm/hardware.h>
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#include <asm/arch/pxa3xx-regs.h>
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#include <asm/arch/ohci.h>
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#include <asm/arch/pm.h>
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#include <asm/arch/dma.h>
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#include <asm/arch/ssp.h>
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/* Ring Oscillator Clock: 60MHz */
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#define RO_CLK 60000000
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#define ACCR_D0CS (1 << 26)
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#define ACCR_PCCE (1 << 11)
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/* crystal frequency to static memory controller multiplier (SMCFS) */
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static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
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/* crystal frequency to HSIO bus frequency multiplier (HSS) */
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static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa3xx_get_clk_frequency_khz(int info)
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{
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unsigned long acsr, xclkcfg;
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unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
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/* Read XCLKCFG register turbo bit */
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__asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
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t = xclkcfg & 0x1;
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acsr = ACSR;
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xl = acsr & 0x1f;
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xn = (acsr >> 8) & 0x7;
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hss = (acsr >> 14) & 0x3;
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XL = xl * BASE_CLK;
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XN = xn * XL;
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ro = acsr & ACCR_D0CS;
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CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
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HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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if (info) {
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pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
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RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
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(ro) ? "" : "in");
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pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
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XL / 1000000, (XL % 1000000) / 10000, xl);
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pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
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XN / 1000000, (XN % 1000000) / 10000, xn,
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(t) ? "" : "in");
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pr_info("HSIO bus clock: %d.%02dMHz\n",
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HSS / 1000000, (HSS % 1000000) / 10000);
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}
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return CLK / 1000;
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}
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/*
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* Return the current static memory controller clock frequency
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* in units of 10kHz
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*/
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unsigned int pxa3xx_get_memclk_frequency_10khz(void)
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{
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unsigned long acsr;
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unsigned int smcfs, clk = 0;
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acsr = ACSR;
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smcfs = (acsr >> 23) & 0x7;
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clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
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return (clk / 10000);
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}
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/*
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* Return the current AC97 clock frequency.
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*/
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static unsigned long clk_pxa3xx_ac97_getrate(struct clk *clk)
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{
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unsigned long rate = 312000000;
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unsigned long ac97_div;
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ac97_div = AC97_DIV;
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/* This may loose precision for some rates but won't for the
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* standard 24.576MHz.
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*/
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rate /= (ac97_div >> 12) & 0x7fff;
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rate *= (ac97_div & 0xfff);
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return rate;
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}
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/*
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* Return the current HSIO bus clock frequency
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*/
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static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
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{
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unsigned long acsr;
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unsigned int hss, hsio_clk;
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acsr = ACSR;
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hss = (acsr >> 14) & 0x3;
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hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
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return hsio_clk;
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}
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static void clk_pxa3xx_cken_enable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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if (clk->cken < 32)
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CKENA |= mask;
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else
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CKENB |= mask;
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}
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static void clk_pxa3xx_cken_disable(struct clk *clk)
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{
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unsigned long mask = 1ul << (clk->cken & 0x1f);
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if (clk->cken < 32)
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CKENA &= ~mask;
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else
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CKENB &= ~mask;
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}
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static const struct clkops clk_pxa3xx_cken_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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};
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static const struct clkops clk_pxa3xx_hsio_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_hsio_getrate,
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};
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static const struct clkops clk_pxa3xx_ac97_ops = {
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.enable = clk_pxa3xx_cken_enable,
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.disable = clk_pxa3xx_cken_disable,
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.getrate = clk_pxa3xx_ac97_getrate,
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};
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static void clk_pout_enable(struct clk *clk)
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{
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OSCC |= OSCC_PEN;
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}
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static void clk_pout_disable(struct clk *clk)
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{
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OSCC &= ~OSCC_PEN;
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}
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static const struct clkops clk_pout_ops = {
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.enable = clk_pout_enable,
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.disable = clk_pout_disable,
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};
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#define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
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{ \
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.name = _name, \
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.dev = _dev, \
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.ops = &clk_pxa3xx_cken_ops, \
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.rate = _rate, \
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.cken = CKEN_##_cken, \
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.delay = _delay, \
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}
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#define PXA3xx_CK(_name, _cken, _ops, _dev) \
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{ \
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.name = _name, \
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.dev = _dev, \
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.ops = _ops, \
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.cken = CKEN_##_cken, \
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}
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static struct clk pxa3xx_clks[] = {
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{
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.name = "CLK_POUT",
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.ops = &clk_pout_ops,
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.rate = 13000000,
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.delay = 70,
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},
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PXA3xx_CK("LCDCLK", LCD, &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
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PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
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PXA3xx_CK("AC97CLK", AC97, &clk_pxa3xx_ac97_ops, NULL),
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PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
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PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
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PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
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PXA3xx_CKEN("I2CCLK", I2C, 32842000, 0, &pxa_device_i2c.dev),
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PXA3xx_CKEN("UDCCLK", UDC, 48000000, 5, &pxa_device_udc.dev),
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PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
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PXA3xx_CKEN("KBDCLK", KEYPAD, 32768, 0, &pxa27x_device_keypad.dev),
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PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
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PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
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PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
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PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
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PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
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PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
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PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
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};
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#ifdef CONFIG_PM
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#define ISRAM_START 0x5c000000
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#define ISRAM_SIZE SZ_256K
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static void __iomem *sram;
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static unsigned long wakeup_src;
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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enum { SLEEP_SAVE_CKENA,
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SLEEP_SAVE_CKENB,
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SLEEP_SAVE_ACCR,
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SLEEP_SAVE_COUNT,
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};
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static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
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{
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SAVE(CKENA);
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SAVE(CKENB);
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SAVE(ACCR);
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}
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static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
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{
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RESTORE(ACCR);
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RESTORE(CKENA);
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RESTORE(CKENB);
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}
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/*
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* Enter a standby mode (S0D1C2 or S0D2C2). Upon wakeup, the dynamic
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* memory controller has to be reinitialised, so we place some code
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* in the SRAM to perform this function.
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*
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* We disable FIQs across the standby - otherwise, we might receive a
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* FIQ while the SDRAM is unavailable.
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*/
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static void pxa3xx_cpu_standby(unsigned int pwrmode)
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{
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extern const char pm_enter_standby_start[], pm_enter_standby_end[];
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void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
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memcpy_toio(sram + 0x8000, pm_enter_standby_start,
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pm_enter_standby_end - pm_enter_standby_start);
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AD2D0SR = ~0;
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AD2D1SR = ~0;
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AD2D0ER = wakeup_src;
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AD2D1ER = 0;
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ASCR = ASCR;
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ARSR = ARSR;
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local_fiq_disable();
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fn(pwrmode);
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local_fiq_enable();
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AD2D0ER = 0;
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AD2D1ER = 0;
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}
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/*
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* NOTE: currently, the OBM (OEM Boot Module) binary comes along with
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* PXA3xx development kits assumes that the resuming process continues
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* with the address stored within the first 4 bytes of SDRAM. The PSPR
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* register is used privately by BootROM and OBM, and _must_ be set to
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* 0x5c014000 for the moment.
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*/
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static void pxa3xx_cpu_pm_suspend(void)
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{
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volatile unsigned long *p = (volatile void *)0xc0000000;
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unsigned long saved_data = *p;
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extern void pxa3xx_cpu_suspend(void);
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extern void pxa3xx_cpu_resume(void);
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/* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
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CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
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CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
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/* clear and setup wakeup source */
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AD3SR = ~0;
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AD3ER = wakeup_src;
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ASCR = ASCR;
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ARSR = ARSR;
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PCFR |= (1u << 13); /* L1_DIS */
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PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
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PSPR = 0x5c014000;
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/* overwrite with the resume address */
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*p = virt_to_phys(pxa3xx_cpu_resume);
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pxa3xx_cpu_suspend();
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*p = saved_data;
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AD3ER = 0;
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}
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static void pxa3xx_cpu_pm_enter(suspend_state_t state)
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{
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/*
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* Don't sleep if no wakeup sources are defined
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*/
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if (wakeup_src == 0) {
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printk(KERN_ERR "Not suspending: no wakeup sources\n");
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return;
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}
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switch (state) {
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case PM_SUSPEND_STANDBY:
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pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
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break;
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case PM_SUSPEND_MEM:
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pxa3xx_cpu_pm_suspend();
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break;
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}
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}
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static int pxa3xx_cpu_pm_valid(suspend_state_t state)
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{
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return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
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}
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static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
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.save_count = SLEEP_SAVE_COUNT,
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.save = pxa3xx_cpu_pm_save,
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.restore = pxa3xx_cpu_pm_restore,
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.valid = pxa3xx_cpu_pm_valid,
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.enter = pxa3xx_cpu_pm_enter,
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};
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static void __init pxa3xx_init_pm(void)
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{
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sram = ioremap(ISRAM_START, ISRAM_SIZE);
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if (!sram) {
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printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
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return;
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}
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/*
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* Since we copy wakeup code into the SRAM, we need to ensure
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* that it is preserved over the low power modes. Note: bit 8
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* is undocumented in the developer manual, but must be set.
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*/
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AD1R |= ADXR_L2 | ADXR_R0;
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AD2R |= ADXR_L2 | ADXR_R0;
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AD3R |= ADXR_L2 | ADXR_R0;
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/*
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* Clear the resume enable registers.
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*/
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AD1D0ER = 0;
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AD2D0ER = 0;
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AD2D1ER = 0;
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AD3ER = 0;
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pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
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}
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static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
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{
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unsigned long flags, mask = 0;
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switch (irq) {
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case IRQ_SSP3:
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mask = ADXER_MFP_WSSP3;
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break;
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case IRQ_MSL:
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mask = ADXER_WMSL0;
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break;
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case IRQ_USBH2:
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case IRQ_USBH1:
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mask = ADXER_WUSBH;
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break;
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case IRQ_KEYPAD:
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mask = ADXER_WKP;
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break;
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case IRQ_AC97:
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mask = ADXER_MFP_WAC97;
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break;
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case IRQ_USIM:
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mask = ADXER_WUSIM0;
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break;
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case IRQ_SSP2:
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mask = ADXER_MFP_WSSP2;
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break;
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case IRQ_I2C:
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mask = ADXER_MFP_WI2C;
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break;
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case IRQ_STUART:
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mask = ADXER_MFP_WUART3;
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break;
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case IRQ_BTUART:
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mask = ADXER_MFP_WUART2;
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break;
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case IRQ_FFUART:
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mask = ADXER_MFP_WUART1;
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break;
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case IRQ_MMC:
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mask = ADXER_MFP_WMMC1;
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break;
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case IRQ_SSP:
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mask = ADXER_MFP_WSSP1;
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break;
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case IRQ_RTCAlrm:
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mask = ADXER_WRTC;
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break;
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case IRQ_SSP4:
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mask = ADXER_MFP_WSSP4;
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break;
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case IRQ_TSI:
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mask = ADXER_WTSI;
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break;
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case IRQ_USIM2:
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mask = ADXER_WUSIM1;
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break;
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case IRQ_MMC2:
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mask = ADXER_MFP_WMMC2;
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break;
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case IRQ_NAND:
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mask = ADXER_MFP_WFLASH;
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break;
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case IRQ_USB2:
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mask = ADXER_WUSB2;
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break;
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case IRQ_WAKEUP0:
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mask = ADXER_WEXTWAKE0;
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break;
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case IRQ_WAKEUP1:
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mask = ADXER_WEXTWAKE1;
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break;
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case IRQ_MMC3:
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mask = ADXER_MFP_GEN12;
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break;
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default:
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return -EINVAL;
|
|
}
|
|
|
|
local_irq_save(flags);
|
|
if (on)
|
|
wakeup_src |= mask;
|
|
else
|
|
wakeup_src &= ~mask;
|
|
local_irq_restore(flags);
|
|
|
|
return 0;
|
|
}
|
|
#else
|
|
static inline void pxa3xx_init_pm(void) {}
|
|
#define pxa3xx_set_wake NULL
|
|
#endif
|
|
|
|
void __init pxa3xx_init_irq(void)
|
|
{
|
|
/* enable CP6 access */
|
|
u32 value;
|
|
__asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
|
|
value |= (1 << 6);
|
|
__asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
|
|
|
|
pxa_init_irq(56, pxa3xx_set_wake);
|
|
pxa_init_gpio(128, NULL);
|
|
}
|
|
|
|
/*
|
|
* device registration specific to PXA3xx.
|
|
*/
|
|
|
|
static struct platform_device *devices[] __initdata = {
|
|
/* &pxa_device_udc, The UDC driver is PXA25x only */
|
|
&pxa_device_ffuart,
|
|
&pxa_device_btuart,
|
|
&pxa_device_stuart,
|
|
&pxa_device_i2s,
|
|
&pxa_device_rtc,
|
|
&pxa27x_device_ssp1,
|
|
&pxa27x_device_ssp2,
|
|
&pxa27x_device_ssp3,
|
|
&pxa3xx_device_ssp4,
|
|
};
|
|
|
|
static struct sys_device pxa3xx_sysdev[] = {
|
|
{
|
|
.cls = &pxa_irq_sysclass,
|
|
}, {
|
|
.cls = &pxa3xx_mfp_sysclass,
|
|
}, {
|
|
.cls = &pxa_gpio_sysclass,
|
|
},
|
|
};
|
|
|
|
static int __init pxa3xx_init(void)
|
|
{
|
|
int i, ret = 0;
|
|
|
|
if (cpu_is_pxa3xx()) {
|
|
/*
|
|
* clear RDH bit every time after reset
|
|
*
|
|
* Note: the last 3 bits DxS are write-1-to-clear so carefully
|
|
* preserve them here in case they will be referenced later
|
|
*/
|
|
ASCR &= ~(ASCR_RDH | ASCR_D1S | ASCR_D2S | ASCR_D3S);
|
|
|
|
clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
|
|
|
|
if ((ret = pxa_init_dma(32)))
|
|
return ret;
|
|
|
|
pxa3xx_init_pm();
|
|
|
|
for (i = 0; i < ARRAY_SIZE(pxa3xx_sysdev); i++) {
|
|
ret = sysdev_register(&pxa3xx_sysdev[i]);
|
|
if (ret)
|
|
pr_err("failed to register sysdev[%d]\n", i);
|
|
}
|
|
|
|
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
postcore_initcall(pxa3xx_init);
|