bcd97aa368
CWB, DP and WB displays tear down sequence must reset 3d_merge, ctl, pingpong_binding, etc. MDP HW blocks. This change fixes the tear down sequence register programming. It also moves flush sw reset before encoder_disable call. That allows CWB tear down to update the flush configuration on primary ctl path. Change-Id: I21c521b39456af4144cf836c65d46a25c985f51d Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
203 lines
5.2 KiB
C
203 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HW_WB_H
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#define _SDE_HW_WB_H
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#include "sde_hw_catalog.h"
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#include "sde_hw_mdss.h"
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#include "sde_hw_top.h"
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#include "sde_hw_util.h"
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struct sde_hw_wb;
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struct sde_hw_wb_cfg {
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struct sde_hw_fmt_layout dest;
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enum sde_intf_mode intf_mode;
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struct sde_rect roi;
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bool is_secure;
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};
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/**
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* enum CDP preload ahead address size
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*/
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enum {
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SDE_WB_CDP_PRELOAD_AHEAD_32,
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SDE_WB_CDP_PRELOAD_AHEAD_64
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};
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/**
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* struct sde_hw_wb_cdp_cfg : CDP configuration
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* @enable: true to enable CDP
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* @ubwc_meta_enable: true to enable ubwc metadata preload
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* @tile_amortize_enable: true to enable amortization control for tile format
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* @preload_ahead: number of request to preload ahead
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* SDE_WB_CDP_PRELOAD_AHEAD_32,
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* SDE_WB_CDP_PRELOAD_AHEAD_64
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*/
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struct sde_hw_wb_cdp_cfg {
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bool enable;
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bool ubwc_meta_enable;
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bool tile_amortize_enable;
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u32 preload_ahead;
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};
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/**
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* struct sde_hw_wb_qos_cfg : Writeback pipe QoS configuration
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* @danger_lut: LUT for generate danger level based on fill level
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* @safe_lut: LUT for generate safe level based on fill level
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* @creq_lut: LUT for generate creq level based on fill level
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* @danger_safe_en: enable danger safe generation
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*/
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struct sde_hw_wb_qos_cfg {
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u32 danger_lut;
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u32 safe_lut;
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u64 creq_lut;
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bool danger_safe_en;
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};
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/**
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*
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* struct sde_hw_wb_ops : Interface to the wb Hw driver functions
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* Assumption is these functions will be called after clocks are enabled
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*/
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struct sde_hw_wb_ops {
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void (*setup_csc_data)(struct sde_hw_wb *ctx,
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struct sde_csc_cfg *data);
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void (*setup_outaddress)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cfg *wb);
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void (*setup_outformat)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cfg *wb);
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void (*setup_rotator)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cfg *wb);
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void (*setup_dither)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cfg *wb);
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void (*setup_cdwn)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cfg *wb);
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void (*setup_trafficshaper)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cfg *wb);
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void (*setup_roi)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cfg *wb);
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/**
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* setup_danger_safe_lut - setup danger safe LUTs
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe QoS configuration
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*/
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void (*setup_danger_safe_lut)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_qos_cfg *cfg);
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/**
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* setup_creq_lut - setup CREQ LUT
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe QoS configuration
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*/
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void (*setup_creq_lut)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_qos_cfg *cfg);
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/**
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* setup_qos_ctrl - setup QoS control
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe QoS configuration
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*/
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void (*setup_qos_ctrl)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_qos_cfg *cfg);
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/**
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* setup_cdp - setup CDP
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* @ctx: Pointer to pipe context
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* @cfg: Pointer to pipe CDP configuration
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*/
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void (*setup_cdp)(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cdp_cfg *cfg);
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/**
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* bind_pingpong_blk - enable/disable the connection with pp
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* @ctx: Pointer to wb context
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* @enable: enable/disable connection
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* @pp: pingpong blk id
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*/
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void (*bind_pingpong_blk)(struct sde_hw_wb *ctx,
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bool enable,
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const enum sde_pingpong pp);
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/**
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* program_cwb_ctrl - program cwb block configp
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* @ctx: Pointer to wb context
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* @pp_idx: Current CWB block index to poram
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* @data_src: Source CWB/PingPong block index
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* @dspp_out: Tap dspp output or default LM output
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* @enable: enable or disable the CWB path to tap the output
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*/
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void (*program_cwb_ctrl)(struct sde_hw_wb *ctx, const enum sde_cwb cwb,
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const enum sde_cwb data_src, bool dspp_out, bool enable);
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};
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/**
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* struct sde_hw_wb : WB driver object
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* @base: hardware block base structure
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* @hw: block hardware details
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* @catalog: back pointer to catalog
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* @mdp: pointer to associated mdp portion of the catalog
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* @idx: hardware index number within type
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* @wb_hw_caps: hardware capabilities
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* @ops: function pointers
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* @hw_mdp: MDP top level hardware block
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* @cwb_hw: CWB control hwio details
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*/
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struct sde_hw_wb {
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struct sde_hw_blk base;
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struct sde_hw_blk_reg_map hw;
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struct sde_mdss_cfg *catalog;
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struct sde_mdp_cfg *mdp;
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/* wb path */
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int idx;
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const struct sde_wb_cfg *caps;
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/* ops */
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struct sde_hw_wb_ops ops;
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struct sde_hw_mdp *hw_mdp;
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struct sde_hw_blk_reg_map cwb_hw;
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};
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/**
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* sde_hw_wb - convert base object sde_hw_base to container
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* @hw: Pointer to base hardware block
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* return: Pointer to hardware block container
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*/
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static inline struct sde_hw_wb *to_sde_hw_wb(struct sde_hw_blk *hw)
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{
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return container_of(hw, struct sde_hw_wb, base);
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}
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/**
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* sde_hw_wb_init(): Initializes and return writeback hw driver object.
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* @idx: wb_path index for which driver object is required
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* @addr: mapped register io address of MDP
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* @m : pointer to mdss catalog data
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* @hw_mdp: pointer to mdp top hw driver object
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*/
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struct sde_hw_wb *sde_hw_wb_init(enum sde_wb idx,
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void __iomem *addr,
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struct sde_mdss_cfg *m,
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struct sde_hw_mdp *hw_mdp);
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/**
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* sde_hw_wb_destroy(): Destroy writeback hw driver object.
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* @hw_wb: Pointer to writeback hw driver object
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*/
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void sde_hw_wb_destroy(struct sde_hw_wb *hw_wb);
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#endif /*_SDE_HW_WB_H */
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