Yujun Zhang 80d06ebb7c disp: pll: limit clock rate of shadow VCO clock ... Limit clock rate of shadow VCO clock as normal VCO clock. For larger bit clock rate gap between switched ones, the clock switching would fail due to mismatched VCO clock rate between normal VCO clock and shadow one. Change-Id: I9d68725de360ac28c243a3ce1800bfb139f39757 Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>		2019-07-25 02:38:39 -07:00
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dp_pll_7nm_util.c	disp: pll: fix sequence as per hardware recommendations	2019-07-12 16:44:05 -07:00
dp_pll_7nm.c	disp: pll: changes to support lito dp clks	2019-06-16 19:18:59 -07:00
dp_pll_7nm.h	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dp_pll_10nm_util.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dp_pll_10nm.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dp_pll_10nm.h	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dp_pll_14nm.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dp_pll_14nm.h	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dp_pll.h	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_20nm_pll_util.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_7nm.c	disp: pll: limit clock rate of shadow VCO clock	2019-07-25 02:38:39 -07:00
dsi_pll_10nm.c	disp: pll: add support for 10nm DSI PLL shadow clock	2019-06-05 16:05:57 +08:00
dsi_pll_14nm_util.c	disp: pll: add support for 10nm DSI PLL shadow clock	2019-06-05 16:05:57 +08:00
dsi_pll_14nm.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_14nm.h	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_20nm.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_28hpm.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_28lpm.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_28nm_util.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_28nm.h	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_8996_util.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_8996.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_8996.h	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll_util.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
dsi_pll.h	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
edp_pll_28hpm.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
hdmi_pll_20nm.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
hdmi_pll_28hpm.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
hdmi_pll_28lpm.c	disp: avoid encoder-connector checks with cont-splash	2019-04-14 22:21:13 -07:00
hdmi_pll_8996.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
hdmi_pll_8998.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
hdmi_pll.h	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
Makefile	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00
pll_drv.c	disp: pll: changes to support lito dp clks	2019-06-16 19:18:59 -07:00
pll_drv.h	Merge "disp: msm: dsi: DSI PHY V4 support of dynamic clock switch"	2019-06-27 03:34:31 -07:00
pll_trace.h	disp: pll: fix TRACE_INCLUDE_FILE path issue	2019-05-14 12:44:55 -07:00
pll_util.c	Display drivers kernel project initial snapshot	2019-04-14 22:20:59 -07:00