9e39ffeff6
Commit 8b798c4d16 broke
alchemy build, fix it. Pointed out by Adrian Bunk.
Signed-off-by: Manuel Lauss <mano@roarinelk.homelinux.net>
Signed-off-by: Jean Delvare <khali@linux-fr.org>
177 lines
5.0 KiB
C
177 lines
5.0 KiB
C
/*
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* AMD Alchemy Semi PB1550 Referrence Board
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* Board Registers defines.
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*
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* Copyright 2004 Embedded Edge LLC.
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* Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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*
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*/
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#ifndef __ASM_PB1550_H
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#define __ASM_PB1550_H
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#include <linux/types.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC3_TX
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#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC3_RX
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#define SPI_PSC_BASE PSC0_BASE_ADDR
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define SMBUS_PSC_BASE PSC2_BASE_ADDR
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#define I2S_PSC_BASE PSC3_BASE_ADDR
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#define BCSR_PHYS_ADDR 0xAF000000
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typedef volatile struct
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{
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/*00*/ u16 whoami;
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u16 reserved0;
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/*04*/ u16 status;
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u16 reserved1;
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/*08*/ u16 switches;
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u16 reserved2;
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/*0C*/ u16 resets;
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u16 reserved3;
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/*10*/ u16 pcmcia;
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u16 reserved4;
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/*14*/ u16 pci;
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u16 reserved5;
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/*18*/ u16 leds;
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u16 reserved6;
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/*1C*/ u16 system;
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u16 reserved7;
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} BCSR;
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static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
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/*
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* Register bit definitions for the BCSRs
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*/
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#define BCSR_WHOAMI_DCID 0x000F
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#define BCSR_WHOAMI_CPLD 0x00F0
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#define BCSR_WHOAMI_BOARD 0x0F00
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#define BCSR_STATUS_PCMCIA0VS 0x0003
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#define BCSR_STATUS_PCMCIA1VS 0x000C
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#define BCSR_STATUS_PCMCIA0FI 0x0010
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#define BCSR_STATUS_PCMCIA1FI 0x0020
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#define BCSR_STATUS_SWAPBOOT 0x0040
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#define BCSR_STATUS_SRAMWIDTH 0x0080
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#define BCSR_STATUS_FLASHBUSY 0x0100
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#define BCSR_STATUS_ROMBUSY 0x0200
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#define BCSR_STATUS_USBOTGID 0x0800
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#define BCSR_STATUS_U0RXD 0x1000
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#define BCSR_STATUS_U1RXD 0x2000
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#define BCSR_STATUS_U3RXD 0x8000
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#define BCSR_SWITCHES_OCTAL 0x00FF
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#define BCSR_SWITCHES_DIP_1 0x0080
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#define BCSR_SWITCHES_DIP_2 0x0040
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#define BCSR_SWITCHES_DIP_3 0x0020
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#define BCSR_SWITCHES_DIP_4 0x0010
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#define BCSR_SWITCHES_DIP_5 0x0008
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#define BCSR_SWITCHES_DIP_6 0x0004
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#define BCSR_SWITCHES_DIP_7 0x0002
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#define BCSR_SWITCHES_DIP_8 0x0001
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#define BCSR_SWITCHES_ROTARY 0x0F00
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#define BCSR_RESETS_PHY0 0x0001
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#define BCSR_RESETS_PHY1 0x0002
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#define BCSR_RESETS_DC 0x0004
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#define BCSR_RESETS_WSC 0x2000
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#define BCSR_RESETS_SPISEL 0x4000
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#define BCSR_RESETS_DMAREQ 0x8000
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#define BCSR_PCMCIA_PC0VPP 0x0003
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#define BCSR_PCMCIA_PC0VCC 0x000C
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#define BCSR_PCMCIA_PC0DRVEN 0x0010
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#define BCSR_PCMCIA_PC0RST 0x0080
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#define BCSR_PCMCIA_PC1VPP 0x0300
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#define BCSR_PCMCIA_PC1VCC 0x0C00
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#define BCSR_PCMCIA_PC1DRVEN 0x1000
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#define BCSR_PCMCIA_PC1RST 0x8000
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#define BCSR_PCI_M66EN 0x0001
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#define BCSR_PCI_M33 0x0100
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#define BCSR_PCI_EXTERNARB 0x0200
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#define BCSR_PCI_GPIO200RST 0x0400
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#define BCSR_PCI_CLKOUT 0x0800
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#define BCSR_PCI_CFGHOST 0x1000
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#define BCSR_LEDS_DECIMALS 0x00FF
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#define BCSR_LEDS_LED0 0x0100
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#define BCSR_LEDS_LED1 0x0200
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#define BCSR_LEDS_LED2 0x0400
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#define BCSR_LEDS_LED3 0x0800
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#define BCSR_SYSTEM_VDDI 0x001F
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#define BCSR_SYSTEM_POWEROFF 0x4000
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#define BCSR_SYSTEM_RESET 0x8000
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#define PCMCIA_MAX_SOCK 1
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#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1)
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/* VPP/VCC */
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#define SET_VCC_VPP(VCC, VPP, SLOT)\
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((((VCC)<<2) | ((VPP)<<0)) << ((SLOT)*8))
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#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
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#define PB1550_BOTH_BANKS
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#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
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#define PB1550_BOOT_ONLY
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#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
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#define PB1550_USER_ONLY
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#endif
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/* Timing values as described in databook, * ns value stripped of
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* lower 2 bits.
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* These defines are here rather than an SOC1550 generic file because
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* the parts chosen on another board may be different and may require
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* different timings.
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*/
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#define NAND_T_H (18 >> 2)
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#define NAND_T_PUL (30 >> 2)
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#define NAND_T_SU (30 >> 2)
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#define NAND_T_WH (30 >> 2)
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/* Bitfield shift amounts */
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#define NAND_T_H_SHIFT 0
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#define NAND_T_PUL_SHIFT 4
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#define NAND_T_SU_SHIFT 8
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#define NAND_T_WH_SHIFT 12
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#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
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((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
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((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
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((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
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#define NAND_CS 1
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/* should be done by yamon */
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#define NAND_STCFG 0x00400005 /* 8-bit NAND */
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#define NAND_STTIME 0x00007774 /* valid for 396MHz SD=2 only */
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#define NAND_STADDR 0x12000FFF /* physical address 0x20000000 */
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#endif /* __ASM_PB1550_H */
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