63dc02bde6
Everything is using sparseirq these days, so we have no need to arbitrarily size nr_irqs ahead of time. The legacy IRQ pre-allocation likewise has no meaning for us, so that's killed off too. We now depend on nr_irqs expansion by the generic hardirq layer instead. It's also worth noting that the majority of boards had completely bogus values for their nr_irqs relative to their CPU and configurations, so this ends up correcting behaviour for quite a few platforms. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
187 lines
5.4 KiB
C
187 lines
5.4 KiB
C
/*
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* arch/sh/mach-cayman/setup.c
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*
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* SH5 Cayman support
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*
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* Copyright (C) 2002 David J. Mckay & Benedict Gaster
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* Copyright (C) 2003 - 2007 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <cpu/irq.h>
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/*
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* Platform Dependent Interrupt Priorities.
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*/
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/* Using defaults defined in irq.h */
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#define RES NO_PRIORITY /* Disabled */
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#define IR0 IRL0_PRIORITY /* IRLs */
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#define IR1 IRL1_PRIORITY
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#define IR2 IRL2_PRIORITY
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#define IR3 IRL3_PRIORITY
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#define PCA INTA_PRIORITY /* PCI Ints */
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#define PCB INTB_PRIORITY
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#define PCC INTC_PRIORITY
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#define PCD INTD_PRIORITY
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#define SER TOP_PRIORITY
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#define ERR TOP_PRIORITY
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#define PW0 TOP_PRIORITY
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#define PW1 TOP_PRIORITY
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#define PW2 TOP_PRIORITY
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#define PW3 TOP_PRIORITY
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#define DM0 NO_PRIORITY /* DMA Ints */
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#define DM1 NO_PRIORITY
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#define DM2 NO_PRIORITY
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#define DM3 NO_PRIORITY
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#define DAE NO_PRIORITY
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#define TU0 TIMER_PRIORITY /* TMU Ints */
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#define TU1 NO_PRIORITY
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#define TU2 NO_PRIORITY
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#define TI2 NO_PRIORITY
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#define ATI NO_PRIORITY /* RTC Ints */
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#define PRI NO_PRIORITY
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#define CUI RTC_PRIORITY
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#define ERI SCIF_PRIORITY /* SCIF Ints */
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#define RXI SCIF_PRIORITY
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#define BRI SCIF_PRIORITY
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#define TXI SCIF_PRIORITY
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#define ITI TOP_PRIORITY /* WDT Ints */
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/* Setup for the SMSC FDC37C935 */
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#define SMSC_SUPERIO_BASE 0x04000000
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#define SMSC_CONFIG_PORT_ADDR 0x3f0
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#define SMSC_INDEX_PORT_ADDR SMSC_CONFIG_PORT_ADDR
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#define SMSC_DATA_PORT_ADDR 0x3f1
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#define SMSC_ENTER_CONFIG_KEY 0x55
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#define SMSC_EXIT_CONFIG_KEY 0xaa
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#define SMCS_LOGICAL_DEV_INDEX 0x07
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#define SMSC_DEVICE_ID_INDEX 0x20
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#define SMSC_DEVICE_REV_INDEX 0x21
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#define SMSC_ACTIVATE_INDEX 0x30
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#define SMSC_PRIMARY_BASE_INDEX 0x60
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#define SMSC_SECONDARY_BASE_INDEX 0x62
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#define SMSC_PRIMARY_INT_INDEX 0x70
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#define SMSC_SECONDARY_INT_INDEX 0x72
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#define SMSC_IDE1_DEVICE 1
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#define SMSC_KEYBOARD_DEVICE 7
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#define SMSC_CONFIG_REGISTERS 8
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#define SMSC_SUPERIO_READ_INDEXED(index) ({ \
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outb((index), SMSC_INDEX_PORT_ADDR); \
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inb(SMSC_DATA_PORT_ADDR); })
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#define SMSC_SUPERIO_WRITE_INDEXED(val, index) ({ \
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outb((index), SMSC_INDEX_PORT_ADDR); \
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outb((val), SMSC_DATA_PORT_ADDR); })
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#define IDE1_PRIMARY_BASE 0x01f0
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#define IDE1_SECONDARY_BASE 0x03f6
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unsigned long smsc_superio_virt;
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int platform_int_priority[NR_INTC_IRQS] = {
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IR0, IR1, IR2, IR3, PCA, PCB, PCC, PCD, /* IRQ 0- 7 */
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RES, RES, RES, RES, SER, ERR, PW3, PW2, /* IRQ 8-15 */
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PW1, PW0, DM0, DM1, DM2, DM3, DAE, RES, /* IRQ 16-23 */
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RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 24-31 */
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TU0, TU1, TU2, TI2, ATI, PRI, CUI, ERI, /* IRQ 32-39 */
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RXI, BRI, TXI, RES, RES, RES, RES, RES, /* IRQ 40-47 */
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RES, RES, RES, RES, RES, RES, RES, RES, /* IRQ 48-55 */
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RES, RES, RES, RES, RES, RES, RES, ITI, /* IRQ 56-63 */
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};
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static int __init smsc_superio_setup(void)
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{
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unsigned char devid, devrev;
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smsc_superio_virt = (unsigned long)ioremap_nocache(SMSC_SUPERIO_BASE, 1024);
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if (!smsc_superio_virt) {
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panic("Unable to remap SMSC SuperIO\n");
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}
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/* Initially the chip is in run state */
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/* Put it into configuration state */
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outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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outb(SMSC_ENTER_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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/* Read device ID info */
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devid = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_ID_INDEX);
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devrev = SMSC_SUPERIO_READ_INDEXED(SMSC_DEVICE_REV_INDEX);
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printk("SMSC SuperIO devid %02x rev %02x\n", devid, devrev);
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/* Select the keyboard device */
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SMSC_SUPERIO_WRITE_INDEXED(SMSC_KEYBOARD_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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/* enable it */
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SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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/* Select the interrupts */
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/* On a PC keyboard is IRQ1, mouse is IRQ12 */
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SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_PRIMARY_INT_INDEX);
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SMSC_SUPERIO_WRITE_INDEXED(12, SMSC_SECONDARY_INT_INDEX);
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#ifdef CONFIG_IDE
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/*
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* Only IDE1 exists on the Cayman
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*/
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/* Power it on */
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SMSC_SUPERIO_WRITE_INDEXED(1 << SMSC_IDE1_DEVICE, 0x22);
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SMSC_SUPERIO_WRITE_INDEXED(SMSC_IDE1_DEVICE, SMCS_LOGICAL_DEV_INDEX);
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SMSC_SUPERIO_WRITE_INDEXED(1, SMSC_ACTIVATE_INDEX);
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SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE >> 8,
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SMSC_PRIMARY_BASE_INDEX + 0);
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SMSC_SUPERIO_WRITE_INDEXED(IDE1_PRIMARY_BASE & 0xff,
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SMSC_PRIMARY_BASE_INDEX + 1);
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SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE >> 8,
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SMSC_SECONDARY_BASE_INDEX + 0);
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SMSC_SUPERIO_WRITE_INDEXED(IDE1_SECONDARY_BASE & 0xff,
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SMSC_SECONDARY_BASE_INDEX + 1);
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SMSC_SUPERIO_WRITE_INDEXED(14, SMSC_PRIMARY_INT_INDEX);
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SMSC_SUPERIO_WRITE_INDEXED(SMSC_CONFIG_REGISTERS,
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SMCS_LOGICAL_DEV_INDEX);
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SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc2); /* GP42 = nIDE1_OE */
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SMSC_SUPERIO_WRITE_INDEXED(0x01, 0xc5); /* GP45 = IDE1_IRQ */
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SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc6); /* GP46 = nIOROP */
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SMSC_SUPERIO_WRITE_INDEXED(0x00, 0xc7); /* GP47 = nIOWOP */
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#endif
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/* Exit the configuration state */
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outb(SMSC_EXIT_CONFIG_KEY, SMSC_CONFIG_PORT_ADDR);
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return 0;
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}
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device_initcall(smsc_superio_setup);
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static void __iomem *cayman_ioport_map(unsigned long port, unsigned int len)
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{
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if (port < 0x400) {
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extern unsigned long smsc_superio_virt;
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return (void __iomem *)((port << 2) | smsc_superio_virt);
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}
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return (void __iomem *)port;
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}
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extern void init_cayman_irq(void);
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static struct sh_machine_vector mv_cayman __initmv = {
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.mv_name = "Hitachi Cayman",
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.mv_ioport_map = cayman_ioport_map,
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.mv_init_irq = init_cayman_irq,
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};
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