e4707dd3e9
This patch adds a Non-cacheable Normal ARM executable memory type, MT_MEMORY_NONCACHED. On OMAP3, this is used for rapid dynamic voltage/frequency scaling in the VDD2 voltage domain. OMAP3's SDRAM controller (SDRC) is in the VDD2 voltage domain, and its clock frequency must change along with voltage. The SDRC clock change code cannot run from SDRAM itself, since SDRAM accesses are paused during the clock change. So the current implementation of the DVFS code executes from OMAP on-chip SRAM, aka "OCM RAM." If the OCM RAM pages are marked as Cacheable, the ARM cache controller will attempt to flush dirty cache lines to the SDRC, so it can fill those lines with OCM RAM instruction code. The problem is that the SDRC is paused during DVFS, and so any SDRAM access causes the ARM MPU subsystem to hang. TI's original solution to this problem was to mark the OCM RAM sections as Strongly Ordered memory, thus preventing caching. This is overkill: since the memory is marked as non-bufferable, OCM RAM writes become needlessly slow. The idea of "Strongly Ordered SRAM" is also conceptually disturbing. Previous LAKML list discussion is here: http://www.spinics.net/lists/arm-kernel/msg54312.html This memory type MT_MEMORY_NONCACHED is used for OCM RAM by a future patch. Cc: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
36 lines
829 B
C
36 lines
829 B
C
/*
|
|
* arch/arm/include/asm/map.h
|
|
*
|
|
* Copyright (C) 1999-2000 Russell King
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
* Page table mapping constructs and function prototypes
|
|
*/
|
|
#include <asm/io.h>
|
|
|
|
struct map_desc {
|
|
unsigned long virtual;
|
|
unsigned long pfn;
|
|
unsigned long length;
|
|
unsigned int type;
|
|
};
|
|
|
|
/* types 0-3 are defined in asm/io.h */
|
|
#define MT_UNCACHED 4
|
|
#define MT_CACHECLEAN 5
|
|
#define MT_MINICLEAN 6
|
|
#define MT_LOW_VECTORS 7
|
|
#define MT_HIGH_VECTORS 8
|
|
#define MT_MEMORY 9
|
|
#define MT_ROM 10
|
|
#define MT_MEMORY_NONCACHED 11
|
|
|
|
#ifdef CONFIG_MMU
|
|
extern void iotable_init(struct map_desc *, int);
|
|
#else
|
|
#define iotable_init(map,num) do { } while (0)
|
|
#endif
|