af777ce42d
For consistenct naming, and to allow us to fix up some confusion in the SH-Mobile clock framework, amongst other places. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
445 lines
11 KiB
C
445 lines
11 KiB
C
/*
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* SH7750/SH7751 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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* Copyright (C) 2006 Jamie Lenehan
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <linux/io.h>
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#include <linux/sh_timer.h>
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#include <linux/serial_sci.h>
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xffc80000,
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.end = 0xffc80000 + 0x58 - 1,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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/* Shared Period/Carry/Alarm IRQ */
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.start = 20,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct plat_sci_port sci_platform_data[] = {
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{
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#ifndef CONFIG_SH_RTS7751R2D
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.mapbase = 0xffe00000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCI,
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.irqs = { 23, 23, 23, 0 },
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}, {
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#endif
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.mapbase = 0xffe80000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 40, 40, 40, 40 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct sh_timer_config tmu0_platform_data = {
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.name = "TMU0",
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.channel_offset = 0x04,
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.timer_bit = 0,
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.clk = "peripheral_clk",
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.clockevent_rating = 200,
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};
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static struct resource tmu0_resources[] = {
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[0] = {
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.name = "TMU0",
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.start = 0xffd80008,
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.end = 0xffd80013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 16,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu0_device = {
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.name = "sh_tmu",
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.id = 0,
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.dev = {
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.platform_data = &tmu0_platform_data,
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},
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.resource = tmu0_resources,
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.num_resources = ARRAY_SIZE(tmu0_resources),
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};
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static struct sh_timer_config tmu1_platform_data = {
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.name = "TMU1",
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clk = "peripheral_clk",
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.clocksource_rating = 200,
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};
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static struct resource tmu1_resources[] = {
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[0] = {
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.name = "TMU1",
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.start = 0xffd80014,
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.end = 0xffd8001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 17,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu1_device = {
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.name = "sh_tmu",
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.id = 1,
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.dev = {
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.platform_data = &tmu1_platform_data,
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},
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.resource = tmu1_resources,
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.num_resources = ARRAY_SIZE(tmu1_resources),
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};
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static struct sh_timer_config tmu2_platform_data = {
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.name = "TMU2",
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.channel_offset = 0x1c,
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.timer_bit = 2,
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.clk = "peripheral_clk",
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};
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static struct resource tmu2_resources[] = {
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[0] = {
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.name = "TMU2",
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.start = 0xffd80020,
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.end = 0xffd8002f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 18,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu2_device = {
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.name = "sh_tmu",
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.id = 2,
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.dev = {
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.platform_data = &tmu2_platform_data,
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},
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.resource = tmu2_resources,
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.num_resources = ARRAY_SIZE(tmu2_resources),
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};
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/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct sh_timer_config tmu3_platform_data = {
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.name = "TMU3",
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.channel_offset = 0x04,
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.timer_bit = 0,
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.clk = "peripheral_clk",
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};
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static struct resource tmu3_resources[] = {
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[0] = {
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.name = "TMU3",
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.start = 0xfe100008,
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.end = 0xfe100013,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 72,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu3_device = {
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.name = "sh_tmu",
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.id = 3,
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.dev = {
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.platform_data = &tmu3_platform_data,
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},
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.resource = tmu3_resources,
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.num_resources = ARRAY_SIZE(tmu3_resources),
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};
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static struct sh_timer_config tmu4_platform_data = {
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.name = "TMU4",
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.channel_offset = 0x10,
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.timer_bit = 1,
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.clk = "peripheral_clk",
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};
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static struct resource tmu4_resources[] = {
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[0] = {
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.name = "TMU4",
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.start = 0xfe100014,
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.end = 0xfe10001f,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = 76,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device tmu4_device = {
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.name = "sh_tmu",
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.id = 4,
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.dev = {
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.platform_data = &tmu4_platform_data,
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},
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.resource = tmu4_resources,
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.num_resources = ARRAY_SIZE(tmu4_resources),
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};
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#endif
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static struct platform_device *sh7750_devices[] __initdata = {
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&rtc_device,
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&sci_device,
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&tmu0_device,
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&tmu1_device,
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&tmu2_device,
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751R)
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&tmu3_device,
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&tmu4_device,
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#endif
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};
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static int __init sh7750_devices_setup(void)
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{
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return platform_add_devices(sh7750_devices,
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ARRAY_SIZE(sh7750_devices));
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}
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__initcall(sh7750_devices_setup);
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static struct platform_device *sh7750_early_devices[] __initdata = {
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&tmu0_device,
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&tmu1_device,
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&tmu2_device,
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751R)
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&tmu3_device,
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&tmu4_device,
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#endif
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};
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void __init plat_early_device_setup(void)
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{
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early_platform_add_devices(sh7750_early_devices,
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ARRAY_SIZE(sh7750_early_devices));
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}
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
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HUDI, GPIOI, DMAC,
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PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
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TMU3, TMU4, TMU0, TMU1, TMU2, RTC, SCI1, SCIF, WDT, REF,
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/* interrupt groups */
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PCIC1,
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};
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static struct intc_vect vectors[] __initdata = {
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INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460),
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INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0),
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INTC_VECT(RTC, 0x4c0),
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INTC_VECT(SCI1, 0x4e0), INTC_VECT(SCI1, 0x500),
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INTC_VECT(SCI1, 0x520), INTC_VECT(SCI1, 0x540),
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INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720),
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INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760),
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INTC_VECT(WDT, 0x560),
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INTC_VECT(REF, 0x580), INTC_VECT(REF, 0x5a0),
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};
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static struct intc_prio_reg prio_registers[] __initdata = {
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{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
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{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
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{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
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{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
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TMU4, TMU3,
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PCIC1, PCIC0_PCISERR } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, NULL,
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NULL, prio_registers, NULL);
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/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7091)
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static struct intc_vect vectors_dma4[] __initdata = {
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INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
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INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
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INTC_VECT(DMAC, 0x6c0),
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};
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static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
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vectors_dma4, NULL,
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NULL, prio_registers, NULL);
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#endif
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/* SH7750R and SH7751R both have 8-channel DMA controllers */
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct intc_vect vectors_dma8[] __initdata = {
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INTC_VECT(DMAC, 0x640), INTC_VECT(DMAC, 0x660),
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INTC_VECT(DMAC, 0x680), INTC_VECT(DMAC, 0x6a0),
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INTC_VECT(DMAC, 0x780), INTC_VECT(DMAC, 0x7a0),
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INTC_VECT(DMAC, 0x7c0), INTC_VECT(DMAC, 0x7e0),
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INTC_VECT(DMAC, 0x6c0),
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};
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static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
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vectors_dma8, NULL,
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NULL, prio_registers, NULL);
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#endif
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/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751) || \
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defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct intc_vect vectors_tmu34[] __initdata = {
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INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
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};
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static struct intc_mask_reg mask_registers[] __initdata = {
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{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, TMU4, TMU3,
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PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
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PCIC1_PCIDMA3, PCIC0_PCISERR } },
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};
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static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
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vectors_tmu34, NULL,
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mask_registers, prio_registers, NULL);
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#endif
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/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
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static struct intc_vect vectors_irlm[] __initdata = {
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INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
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INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
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};
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static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
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NULL, prio_registers, NULL);
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/* SH7751 and SH7751R both have PCI */
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#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
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static struct intc_vect vectors_pci[] __initdata = {
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INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
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INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
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INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
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INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
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};
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static struct intc_group groups_pci[] __initdata = {
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INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
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};
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static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
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mask_registers, prio_registers, NULL);
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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defined(CONFIG_CPU_SUBTYPE_SH7091)
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void __init plat_irq_setup(void)
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{
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/*
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* same vectors for SH7750, SH7750S and SH7091 except for IRLM,
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* see below..
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*/
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register_intc_controller(&intc_desc);
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register_intc_controller(&intc_desc_dma4);
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}
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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register_intc_controller(&intc_desc_dma8);
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register_intc_controller(&intc_desc_tmu34);
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}
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7751)
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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register_intc_controller(&intc_desc_dma4);
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register_intc_controller(&intc_desc_tmu34);
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register_intc_controller(&intc_desc_pci);
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}
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
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void __init plat_irq_setup(void)
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{
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register_intc_controller(&intc_desc);
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register_intc_controller(&intc_desc_dma8);
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register_intc_controller(&intc_desc_tmu34);
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register_intc_controller(&intc_desc_pci);
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}
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#endif
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#define INTC_ICR 0xffd00000UL
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#define INTC_ICR_IRLM (1<<7)
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void __init plat_irq_setup_pins(int mode)
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{
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#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
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BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
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return;
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#endif
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switch (mode) {
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case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
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ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
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register_intc_controller(&intc_desc_irlm);
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break;
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default:
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BUG();
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}
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}
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