ab9683ca81
We don't use any CPM devices on these boards, but the muram node on these chips is different from the 8560, so it's helpful to people working with custom boards based on these chips. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
280 lines
6.2 KiB
Plaintext
280 lines
6.2 KiB
Plaintext
/*
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* MPC8555 CDS Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8555CDS";
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compatible = "MPC8555CDS", "MPC85xxCDS";
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8555@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <8000>; // L1, 32K
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i-cache-size = <8000>; // L1, 32K
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timebase-frequency = <0>; // 33 MHz, from uboot
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bus-frequency = <0>; // 166 MHz
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clock-frequency = <0>; // 825 MHz, from uboot
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 08000000>; // 128M at 0x0
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};
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soc8555@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00001000>; // CCSRBAR 1M
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bus-frequency = <0>;
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memory-controller@2000 {
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compatible = "fsl,8555-memory-controller";
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reg = <2000 1000>;
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interrupt-parent = <&mpic>;
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interrupts = <12 2>;
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};
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l2-cache-controller@20000 {
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compatible = "fsl,8555-l2-cache-controller";
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reg = <20000 1000>;
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cache-line-size = <20>; // 32 bytes
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cache-size = <40000>; // L2, 256K
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interrupt-parent = <&mpic>;
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interrupts = <10 2>;
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};
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i2c@3000 {
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device_type = "i2c";
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <2b 2>;
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interrupt-parent = <&mpic>;
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dfsrr;
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};
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mdio@24520 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "mdio";
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compatible = "gianfar";
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reg = <24520 20>;
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phy0: ethernet-phy@0 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1>;
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reg = <1>;
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device_type = "ethernet-phy";
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};
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};
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ethernet@24000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <24000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <1d 2 1e 2 22 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy0>;
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};
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ethernet@25000 {
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#address-cells = <1>;
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#size-cells = <0>;
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device_type = "network";
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model = "TSEC";
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compatible = "gianfar";
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reg = <25000 1000>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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interrupts = <23 2 24 2 28 2>;
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interrupt-parent = <&mpic>;
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phy-handle = <&phy1>;
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};
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serial@4500 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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serial@4600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>; // reg base, size
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clock-frequency = <0>; // should we fill in in uboot?
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interrupts = <2a 2>;
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interrupt-parent = <&mpic>;
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};
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mpic: pic@40000 {
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clock-frequency = <0>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <40000 40000>;
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compatible = "chrp,open-pic";
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device_type = "open-pic";
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big-endian;
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};
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cpm@919c0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8555-cpm", "fsl,cpm2";
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reg = <919c0 30>;
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ranges;
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muram@80000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 80000 10000>;
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data@0 {
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compatible = "fsl,cpm-muram-data";
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reg = <0 2000 9000 1000>;
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};
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};
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brg@919f0 {
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compatible = "fsl,mpc8555-brg",
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"fsl,cpm2-brg",
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"fsl,cpm-brg";
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reg = <919f0 10 915f0 10>;
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};
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cpmpic: pic@90c00 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <2e 2>;
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interrupt-parent = <&mpic>;
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reg = <90c00 80>;
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compatible = "fsl,mpc8555-cpm-pic", "fsl,cpm2-pic";
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};
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};
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};
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pci1: pci@e0008000 {
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interrupt-map-mask = <1f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x10 */
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08000 0 0 1 &mpic 0 1
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08000 0 0 2 &mpic 1 1
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08000 0 0 3 &mpic 2 1
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08000 0 0 4 &mpic 3 1
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/* IDSEL 0x11 */
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08800 0 0 1 &mpic 0 1
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08800 0 0 2 &mpic 1 1
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08800 0 0 3 &mpic 2 1
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08800 0 0 4 &mpic 3 1
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/* IDSEL 0x12 (Slot 1) */
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09000 0 0 1 &mpic 0 1
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09000 0 0 2 &mpic 1 1
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09000 0 0 3 &mpic 2 1
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09000 0 0 4 &mpic 3 1
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/* IDSEL 0x13 (Slot 2) */
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09800 0 0 1 &mpic 1 1
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09800 0 0 2 &mpic 2 1
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09800 0 0 3 &mpic 3 1
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09800 0 0 4 &mpic 0 1
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/* IDSEL 0x14 (Slot 3) */
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0a000 0 0 1 &mpic 2 1
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0a000 0 0 2 &mpic 3 1
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0a000 0 0 3 &mpic 0 1
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0a000 0 0 4 &mpic 1 1
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/* IDSEL 0x15 (Slot 4) */
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0a800 0 0 1 &mpic 3 1
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0a800 0 0 2 &mpic 0 1
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0a800 0 0 3 &mpic 1 1
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0a800 0 0 4 &mpic 2 1
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/* Bus 1 (Tundra Bridge) */
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/* IDSEL 0x12 (ISA bridge) */
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19000 0 0 1 &mpic 0 1
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19000 0 0 2 &mpic 1 1
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19000 0 0 3 &mpic 2 1
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19000 0 0 4 &mpic 3 1>;
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interrupt-parent = <&mpic>;
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interrupts = <18 2>;
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bus-range = <0 0>;
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ranges = <02000000 0 80000000 80000000 0 20000000
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01000000 0 00000000 e2000000 0 00100000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008000 1000>;
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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i8259@19000 {
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interrupt-controller;
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device_type = "interrupt-controller";
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reg = <19000 0 0 0 1>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <1>;
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interrupt-parent = <&pci1>;
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};
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};
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pci@e0009000 {
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x15 */
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a800 0 0 1 &mpic b 1
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a800 0 0 2 &mpic b 1
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a800 0 0 3 &mpic b 1
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a800 0 0 4 &mpic b 1>;
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interrupt-parent = <&mpic>;
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interrupts = <19 2>;
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bus-range = <0 0>;
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ranges = <02000000 0 a0000000 a0000000 0 20000000
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01000000 0 00000000 e3000000 0 00100000>;
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clock-frequency = <3f940aa>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0009000 1000>;
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compatible = "fsl,mpc8540-pci";
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device_type = "pci";
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};
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};
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