8ea6091f50
First phase in introducing ACPI support to SN. In this phase, when running with an ACPI capable PROM, the DSDT will define the root busses and all SN nodes (SGIHUB, SGITIO). An ACPI bus driver will be registered for the node devices, with the acpi_pci_root_driver being used for the root busses. An ACPI vendor descriptor is now used to pass platform specific information for both nodes and busses, eliminating the need for the current SAL calls. Also, with ACPI support, SN fixup code is no longer needed to initiate the PCI bus scans, as the acpi_pci_root_driver does that. However, to maintain backward compatibility with non-ACPI capable PROMs, none of the current 'fixup' code can been deleted, though much restructuring has been done. For example, the bulk of the code in io_common.c is relocated code that is now common regardless of what PROM is running, while io_acpi_init.c and io_init.c contain routines specific to an ACPI or non ACPI capable PROM respectively. A new pci bus fixup platform vector has been created to provide a hook for invoking platform specific bus fixup from pcibios_fixup_bus(). The size of io_space[] has been increased to support systems with large IO configurations. Signed-off-by: John Keller <jpk@sgi.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
82 lines
2.2 KiB
C
82 lines
2.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2000-2003, 2006 Silicon Graphics, Inc. All rights reserved.
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*/
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#include <linux/module.h>
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#include <linux/acpi.h>
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#include <asm/io.h>
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#include <asm/delay.h>
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#include <asm/vga.h>
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#include <asm/sn/nodepda.h>
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#include <asm/sn/simulator.h>
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#include <asm/sn/pda.h>
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#include <asm/sn/sn_cpuid.h>
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#include <asm/sn/shub_mmr.h>
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#include <asm/sn/acpi.h>
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#define IS_LEGACY_VGA_IOPORT(p) \
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(((p) >= 0x3b0 && (p) <= 0x3bb) || ((p) >= 0x3c0 && (p) <= 0x3df))
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/**
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* sn_io_addr - convert an in/out port to an i/o address
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* @port: port to convert
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*
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* Legacy in/out instructions are converted to ld/st instructions
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* on IA64. This routine will convert a port number into a valid
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* SN i/o address. Used by sn_in*() and sn_out*().
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*/
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void *sn_io_addr(unsigned long port)
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{
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if (!IS_RUNNING_ON_SIMULATOR()) {
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if (IS_LEGACY_VGA_IOPORT(port))
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return (__ia64_mk_io_addr(port));
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/* On sn2, legacy I/O ports don't point at anything */
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if (port < (64 * 1024))
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return NULL;
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if (SN_ACPI_BASE_SUPPORT())
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return (__ia64_mk_io_addr(port));
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else
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return ((void *)(port | __IA64_UNCACHED_OFFSET));
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} else {
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/* but the simulator uses them... */
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unsigned long addr;
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/*
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* word align port, but need more than 10 bits
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* for accessing registers in bedrock local block
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* (so we don't do port&0xfff)
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*/
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addr = (is_shub2() ? 0xc00000028c000000UL : 0xc0000087cc000000UL) | ((port >> 2) << 12);
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if ((port >= 0x1f0 && port <= 0x1f7) || port == 0x3f6 || port == 0x3f7)
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addr |= port;
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return (void *)addr;
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}
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}
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EXPORT_SYMBOL(sn_io_addr);
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/**
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* __sn_mmiowb - I/O space memory barrier
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*
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* See include/asm-ia64/io.h and Documentation/DocBook/deviceiobook.tmpl
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* for details.
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*
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* On SN2, we wait for the PIO_WRITE_STATUS SHub register to clear.
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* See PV 871084 for details about the WAR about zero value.
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*
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*/
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void __sn_mmiowb(void)
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{
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volatile unsigned long *adr = pda->pio_write_status_addr;
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unsigned long val = pda->pio_write_status_val;
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while ((*adr & SH_PIO_WRITE_STATUS_PENDING_WRITE_COUNT_MASK) != val)
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cpu_relax();
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}
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EXPORT_SYMBOL(__sn_mmiowb);
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