2700f8b048
Add a flag to struct txdata_entry_desc that specifies whether an ack for the frame is to be expected. Use this flag to set the ACK bit in the tx descriptor. Previously, the ACK bit could be set incorrectly on CTS-to-self frames, so they caused retries and were reported to be failed in the txdone handlers. Signed-off-by: Mattias Nissler <mattias.nissler@gmx.de> Signed-off-by: Ivo van Doorn <IvDoorn@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2156 lines
64 KiB
C
2156 lines
64 KiB
C
/*
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Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the
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Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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/*
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Module: rt73usb
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Abstract: rt73usb device specific routines.
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Supported chipsets: rt2571W & rt2671.
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*/
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/*
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* Set enviroment defines for rt2x00.h
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*/
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#define DRV_NAME "rt73usb"
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/usb.h>
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#include "rt2x00.h"
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#include "rt2x00usb.h"
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#include "rt73usb.h"
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/*
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* Register access.
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* All access to the CSR registers will go through the methods
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* rt73usb_register_read and rt73usb_register_write.
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* BBP and RF register require indirect register access,
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* and use the CSR registers BBPCSR and RFCSR to achieve this.
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* These indirect registers work with busy bits,
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* and we will try maximal REGISTER_BUSY_COUNT times to access
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* the register while taking a REGISTER_BUSY_DELAY us delay
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* between each attampt. When the busy bit is still set at that time,
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* the access attempt is considered to have failed,
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* and we will print an error.
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* The _lock versions must be used if you already hold the usb_cache_mutex
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*/
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static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
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const unsigned int offset, u32 *value)
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{
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__le32 reg;
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rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
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USB_VENDOR_REQUEST_IN, offset,
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®, sizeof(u32), REGISTER_TIMEOUT);
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*value = le32_to_cpu(reg);
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}
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static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
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const unsigned int offset, u32 *value)
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{
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__le32 reg;
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rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
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USB_VENDOR_REQUEST_IN, offset,
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®, sizeof(u32), REGISTER_TIMEOUT);
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*value = le32_to_cpu(reg);
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}
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static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
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const unsigned int offset,
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void *value, const u32 length)
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{
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int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
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rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
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USB_VENDOR_REQUEST_IN, offset,
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value, length, timeout);
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}
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static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
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const unsigned int offset, u32 value)
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{
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__le32 reg = cpu_to_le32(value);
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rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
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USB_VENDOR_REQUEST_OUT, offset,
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®, sizeof(u32), REGISTER_TIMEOUT);
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}
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static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
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const unsigned int offset, u32 value)
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{
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__le32 reg = cpu_to_le32(value);
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rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
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USB_VENDOR_REQUEST_OUT, offset,
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®, sizeof(u32), REGISTER_TIMEOUT);
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}
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static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
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const unsigned int offset,
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void *value, const u32 length)
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{
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int timeout = REGISTER_TIMEOUT * (length / sizeof(u32));
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rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
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USB_VENDOR_REQUEST_OUT, offset,
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value, length, timeout);
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}
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static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
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{
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u32 reg;
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unsigned int i;
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for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
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rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, ®);
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if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
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break;
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udelay(REGISTER_BUSY_DELAY);
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}
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return reg;
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}
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static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
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const unsigned int word, const u8 value)
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{
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u32 reg;
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mutex_lock(&rt2x00dev->usb_cache_mutex);
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/*
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* Wait until the BBP becomes ready.
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*/
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reg = rt73usb_bbp_check(rt2x00dev);
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if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
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ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
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mutex_unlock(&rt2x00dev->usb_cache_mutex);
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return;
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}
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/*
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* Write the data into the BBP.
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*/
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reg = 0;
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rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
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rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
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rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
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rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
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rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
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mutex_unlock(&rt2x00dev->usb_cache_mutex);
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}
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static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
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const unsigned int word, u8 *value)
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{
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u32 reg;
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mutex_lock(&rt2x00dev->usb_cache_mutex);
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/*
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* Wait until the BBP becomes ready.
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*/
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reg = rt73usb_bbp_check(rt2x00dev);
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if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
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ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
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mutex_unlock(&rt2x00dev->usb_cache_mutex);
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return;
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}
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/*
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* Write the request into the BBP.
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*/
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reg = 0;
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rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
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rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
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rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
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rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
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/*
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* Wait until the BBP becomes ready.
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*/
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reg = rt73usb_bbp_check(rt2x00dev);
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if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
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ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
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*value = 0xff;
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return;
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}
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*value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
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mutex_unlock(&rt2x00dev->usb_cache_mutex);
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}
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static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
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const unsigned int word, const u32 value)
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{
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u32 reg;
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unsigned int i;
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if (!word)
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return;
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mutex_lock(&rt2x00dev->usb_cache_mutex);
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for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
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rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, ®);
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if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
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goto rf_write;
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udelay(REGISTER_BUSY_DELAY);
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}
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mutex_unlock(&rt2x00dev->usb_cache_mutex);
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ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
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return;
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rf_write:
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reg = 0;
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rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
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/*
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* RF5225 and RF2527 contain 21 bits per RF register value,
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* all others contain 20 bits.
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*/
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rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS,
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20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
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rt2x00_rf(&rt2x00dev->chip, RF2527)));
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rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
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rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
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rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
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rt2x00_rf_write(rt2x00dev, word, value);
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mutex_unlock(&rt2x00dev->usb_cache_mutex);
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}
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#ifdef CONFIG_RT2X00_LIB_DEBUGFS
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#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
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static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
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const unsigned int word, u32 *data)
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{
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rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
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}
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static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
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const unsigned int word, u32 data)
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{
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rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
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}
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static const struct rt2x00debug rt73usb_rt2x00debug = {
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.owner = THIS_MODULE,
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.csr = {
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.read = rt73usb_read_csr,
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.write = rt73usb_write_csr,
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.word_size = sizeof(u32),
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.word_count = CSR_REG_SIZE / sizeof(u32),
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},
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.eeprom = {
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.read = rt2x00_eeprom_read,
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.write = rt2x00_eeprom_write,
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.word_size = sizeof(u16),
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.word_count = EEPROM_SIZE / sizeof(u16),
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},
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.bbp = {
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.read = rt73usb_bbp_read,
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.write = rt73usb_bbp_write,
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.word_size = sizeof(u8),
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.word_count = BBP_SIZE / sizeof(u8),
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},
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.rf = {
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.read = rt2x00_rf_read,
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.write = rt73usb_rf_write,
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.word_size = sizeof(u32),
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.word_count = RF_SIZE / sizeof(u32),
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},
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};
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#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
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/*
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* Configuration handlers.
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*/
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static void rt73usb_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
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{
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u32 tmp;
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tmp = le32_to_cpu(mac[1]);
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rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
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mac[1] = cpu_to_le32(tmp);
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rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
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(2 * sizeof(__le32)));
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}
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static void rt73usb_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
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{
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u32 tmp;
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tmp = le32_to_cpu(bssid[1]);
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rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
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bssid[1] = cpu_to_le32(tmp);
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rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
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(2 * sizeof(__le32)));
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}
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static void rt73usb_config_type(struct rt2x00_dev *rt2x00dev, const int type,
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const int tsf_sync)
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{
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u32 reg;
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/*
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* Clear current synchronisation setup.
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* For the Beacon base registers we only need to clear
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* the first byte since that byte contains the VALID and OWNER
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* bits which (when set to 0) will invalidate the entire beacon.
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*/
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rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
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rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
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rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
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rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
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rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
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/*
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* Enable synchronisation.
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*/
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rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
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rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
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rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
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rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
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rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, tsf_sync);
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rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
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}
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static void rt73usb_config_preamble(struct rt2x00_dev *rt2x00dev,
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const int short_preamble,
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const int ack_timeout,
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const int ack_consume_time)
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{
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u32 reg;
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/*
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* When in atomic context, reschedule and let rt2x00lib
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* call this function again.
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*/
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if (in_atomic()) {
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queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->config_work);
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return;
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}
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rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
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rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
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rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
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rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
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rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
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!!short_preamble);
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rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
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}
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|
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static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
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const int basic_rate_mask)
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{
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rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
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}
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|
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static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
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struct rf_channel *rf, const int txpower)
|
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{
|
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u8 r3;
|
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u8 r94;
|
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u8 smart;
|
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|
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rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
|
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rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
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|
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smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
|
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rt2x00_rf(&rt2x00dev->chip, RF2527));
|
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|
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rt73usb_bbp_read(rt2x00dev, 3, &r3);
|
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rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
|
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rt73usb_bbp_write(rt2x00dev, 3, r3);
|
|
|
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r94 = 6;
|
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if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
|
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r94 += txpower - MAX_TXPOWER;
|
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else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
|
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r94 += txpower;
|
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rt73usb_bbp_write(rt2x00dev, 94, r94);
|
|
|
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rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
|
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rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
|
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rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
|
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rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
|
|
|
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rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
|
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rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
|
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rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
|
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rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
|
|
|
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rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
|
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rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
|
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rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
|
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rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
|
|
|
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udelay(10);
|
|
}
|
|
|
|
static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
|
|
const int txpower)
|
|
{
|
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struct rf_channel rf;
|
|
|
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rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
|
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rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
|
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rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
|
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rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
|
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|
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rt73usb_config_channel(rt2x00dev, &rf, txpower);
|
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}
|
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|
|
static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
|
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struct antenna_setup *ant)
|
|
{
|
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u8 r3;
|
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u8 r4;
|
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u8 r77;
|
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u8 temp;
|
|
|
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rt73usb_bbp_read(rt2x00dev, 3, &r3);
|
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rt73usb_bbp_read(rt2x00dev, 4, &r4);
|
|
rt73usb_bbp_read(rt2x00dev, 77, &r77);
|
|
|
|
rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
|
|
|
|
/*
|
|
* Configure the RX antenna.
|
|
*/
|
|
switch (ant->rx) {
|
|
case ANTENNA_HW_DIVERSITY:
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
|
|
temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
|
|
&& (rt2x00dev->curr_hwmode != HWMODE_A);
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
|
|
break;
|
|
case ANTENNA_A:
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
|
|
if (rt2x00dev->curr_hwmode == HWMODE_A)
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
|
|
else
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
|
|
break;
|
|
case ANTENNA_SW_DIVERSITY:
|
|
/*
|
|
* NOTE: We should never come here because rt2x00lib is
|
|
* supposed to catch this and send us the correct antenna
|
|
* explicitely. However we are nog going to bug about this.
|
|
* Instead, just default to antenna B.
|
|
*/
|
|
case ANTENNA_B:
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
|
|
if (rt2x00dev->curr_hwmode == HWMODE_A)
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
|
|
else
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
|
|
break;
|
|
}
|
|
|
|
rt73usb_bbp_write(rt2x00dev, 77, r77);
|
|
rt73usb_bbp_write(rt2x00dev, 3, r3);
|
|
rt73usb_bbp_write(rt2x00dev, 4, r4);
|
|
}
|
|
|
|
static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
|
|
struct antenna_setup *ant)
|
|
{
|
|
u8 r3;
|
|
u8 r4;
|
|
u8 r77;
|
|
|
|
rt73usb_bbp_read(rt2x00dev, 3, &r3);
|
|
rt73usb_bbp_read(rt2x00dev, 4, &r4);
|
|
rt73usb_bbp_read(rt2x00dev, 77, &r77);
|
|
|
|
rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
|
|
!test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
|
|
|
|
/*
|
|
* Configure the RX antenna.
|
|
*/
|
|
switch (ant->rx) {
|
|
case ANTENNA_HW_DIVERSITY:
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
|
|
break;
|
|
case ANTENNA_A:
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
|
break;
|
|
case ANTENNA_SW_DIVERSITY:
|
|
/*
|
|
* NOTE: We should never come here because rt2x00lib is
|
|
* supposed to catch this and send us the correct antenna
|
|
* explicitely. However we are nog going to bug about this.
|
|
* Instead, just default to antenna B.
|
|
*/
|
|
case ANTENNA_B:
|
|
rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
|
|
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
|
|
break;
|
|
}
|
|
|
|
rt73usb_bbp_write(rt2x00dev, 77, r77);
|
|
rt73usb_bbp_write(rt2x00dev, 3, r3);
|
|
rt73usb_bbp_write(rt2x00dev, 4, r4);
|
|
}
|
|
|
|
struct antenna_sel {
|
|
u8 word;
|
|
/*
|
|
* value[0] -> non-LNA
|
|
* value[1] -> LNA
|
|
*/
|
|
u8 value[2];
|
|
};
|
|
|
|
static const struct antenna_sel antenna_sel_a[] = {
|
|
{ 96, { 0x58, 0x78 } },
|
|
{ 104, { 0x38, 0x48 } },
|
|
{ 75, { 0xfe, 0x80 } },
|
|
{ 86, { 0xfe, 0x80 } },
|
|
{ 88, { 0xfe, 0x80 } },
|
|
{ 35, { 0x60, 0x60 } },
|
|
{ 97, { 0x58, 0x58 } },
|
|
{ 98, { 0x58, 0x58 } },
|
|
};
|
|
|
|
static const struct antenna_sel antenna_sel_bg[] = {
|
|
{ 96, { 0x48, 0x68 } },
|
|
{ 104, { 0x2c, 0x3c } },
|
|
{ 75, { 0xfe, 0x80 } },
|
|
{ 86, { 0xfe, 0x80 } },
|
|
{ 88, { 0xfe, 0x80 } },
|
|
{ 35, { 0x50, 0x50 } },
|
|
{ 97, { 0x48, 0x48 } },
|
|
{ 98, { 0x48, 0x48 } },
|
|
};
|
|
|
|
static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
|
|
struct antenna_setup *ant)
|
|
{
|
|
const struct antenna_sel *sel;
|
|
unsigned int lna;
|
|
unsigned int i;
|
|
u32 reg;
|
|
|
|
if (rt2x00dev->curr_hwmode == HWMODE_A) {
|
|
sel = antenna_sel_a;
|
|
lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
|
|
} else {
|
|
sel = antenna_sel_bg;
|
|
lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
|
|
rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
|
|
|
|
rt73usb_register_read(rt2x00dev, PHY_CSR0, ®);
|
|
|
|
rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
|
|
(rt2x00dev->curr_hwmode == HWMODE_B ||
|
|
rt2x00dev->curr_hwmode == HWMODE_G));
|
|
rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
|
|
(rt2x00dev->curr_hwmode == HWMODE_A));
|
|
|
|
rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
|
|
|
|
if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
|
|
rt2x00_rf(&rt2x00dev->chip, RF5225))
|
|
rt73usb_config_antenna_5x(rt2x00dev, ant);
|
|
else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
|
|
rt2x00_rf(&rt2x00dev->chip, RF2527))
|
|
rt73usb_config_antenna_2x(rt2x00dev, ant);
|
|
}
|
|
|
|
static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
|
|
struct rt2x00lib_conf *libconf)
|
|
{
|
|
u32 reg;
|
|
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
|
|
rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR8, ®);
|
|
rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
|
|
rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
|
|
rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
|
|
libconf->conf->beacon_int * 16);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
}
|
|
|
|
static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
|
|
const unsigned int flags,
|
|
struct rt2x00lib_conf *libconf)
|
|
{
|
|
if (flags & CONFIG_UPDATE_PHYMODE)
|
|
rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
|
|
if (flags & CONFIG_UPDATE_CHANNEL)
|
|
rt73usb_config_channel(rt2x00dev, &libconf->rf,
|
|
libconf->conf->power_level);
|
|
if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
|
|
rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
|
|
if (flags & CONFIG_UPDATE_ANTENNA)
|
|
rt73usb_config_antenna(rt2x00dev, &libconf->ant);
|
|
if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
|
|
rt73usb_config_duration(rt2x00dev, libconf);
|
|
}
|
|
|
|
/*
|
|
* LED functions.
|
|
*/
|
|
static void rt73usb_enable_led(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
u32 reg;
|
|
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR14, ®);
|
|
rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
|
|
rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR14, reg);
|
|
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
|
|
(rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
|
|
(rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
|
|
|
|
rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
|
|
rt2x00dev->led_reg, REGISTER_TIMEOUT);
|
|
}
|
|
|
|
static void rt73usb_disable_led(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 0);
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
|
|
|
|
rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, 0x0000,
|
|
rt2x00dev->led_reg, REGISTER_TIMEOUT);
|
|
}
|
|
|
|
static void rt73usb_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
|
|
{
|
|
u32 led;
|
|
|
|
if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
|
|
return;
|
|
|
|
/*
|
|
* Led handling requires a positive value for the rssi,
|
|
* to do that correctly we need to add the correction.
|
|
*/
|
|
rssi += rt2x00dev->rssi_offset;
|
|
|
|
if (rssi <= 30)
|
|
led = 0;
|
|
else if (rssi <= 39)
|
|
led = 1;
|
|
else if (rssi <= 49)
|
|
led = 2;
|
|
else if (rssi <= 53)
|
|
led = 3;
|
|
else if (rssi <= 63)
|
|
led = 4;
|
|
else
|
|
led = 5;
|
|
|
|
rt2x00usb_vendor_request_sw(rt2x00dev, USB_LED_CONTROL, led,
|
|
rt2x00dev->led_reg, REGISTER_TIMEOUT);
|
|
}
|
|
|
|
/*
|
|
* Link tuning
|
|
*/
|
|
static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
|
|
struct link_qual *qual)
|
|
{
|
|
u32 reg;
|
|
|
|
/*
|
|
* Update FCS error count from register.
|
|
*/
|
|
rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
|
|
qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
|
|
|
|
/*
|
|
* Update False CCA count from register.
|
|
*/
|
|
rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
|
|
qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
|
|
}
|
|
|
|
static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
rt73usb_bbp_write(rt2x00dev, 17, 0x20);
|
|
rt2x00dev->link.vgc_level = 0x20;
|
|
}
|
|
|
|
static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
|
|
u8 r17;
|
|
u8 up_bound;
|
|
u8 low_bound;
|
|
|
|
/*
|
|
* Update Led strength
|
|
*/
|
|
rt73usb_activity_led(rt2x00dev, rssi);
|
|
|
|
rt73usb_bbp_read(rt2x00dev, 17, &r17);
|
|
|
|
/*
|
|
* Determine r17 bounds.
|
|
*/
|
|
if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
|
|
low_bound = 0x28;
|
|
up_bound = 0x48;
|
|
|
|
if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
|
|
low_bound += 0x10;
|
|
up_bound += 0x10;
|
|
}
|
|
} else {
|
|
if (rssi > -82) {
|
|
low_bound = 0x1c;
|
|
up_bound = 0x40;
|
|
} else if (rssi > -84) {
|
|
low_bound = 0x1c;
|
|
up_bound = 0x20;
|
|
} else {
|
|
low_bound = 0x1c;
|
|
up_bound = 0x1c;
|
|
}
|
|
|
|
if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
|
|
low_bound += 0x14;
|
|
up_bound += 0x10;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Special big-R17 for very short distance
|
|
*/
|
|
if (rssi > -35) {
|
|
if (r17 != 0x60)
|
|
rt73usb_bbp_write(rt2x00dev, 17, 0x60);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Special big-R17 for short distance
|
|
*/
|
|
if (rssi >= -58) {
|
|
if (r17 != up_bound)
|
|
rt73usb_bbp_write(rt2x00dev, 17, up_bound);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Special big-R17 for middle-short distance
|
|
*/
|
|
if (rssi >= -66) {
|
|
low_bound += 0x10;
|
|
if (r17 != low_bound)
|
|
rt73usb_bbp_write(rt2x00dev, 17, low_bound);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Special mid-R17 for middle distance
|
|
*/
|
|
if (rssi >= -74) {
|
|
if (r17 != (low_bound + 0x10))
|
|
rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Special case: Change up_bound based on the rssi.
|
|
* Lower up_bound when rssi is weaker then -74 dBm.
|
|
*/
|
|
up_bound -= 2 * (-74 - rssi);
|
|
if (low_bound > up_bound)
|
|
up_bound = low_bound;
|
|
|
|
if (r17 > up_bound) {
|
|
rt73usb_bbp_write(rt2x00dev, 17, up_bound);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* r17 does not yet exceed upper limit, continue and base
|
|
* the r17 tuning on the false CCA count.
|
|
*/
|
|
if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
|
|
r17 += 4;
|
|
if (r17 > up_bound)
|
|
r17 = up_bound;
|
|
rt73usb_bbp_write(rt2x00dev, 17, r17);
|
|
} else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
|
|
r17 -= 4;
|
|
if (r17 < low_bound)
|
|
r17 = low_bound;
|
|
rt73usb_bbp_write(rt2x00dev, 17, r17);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Firmware name function.
|
|
*/
|
|
static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
return FIRMWARE_RT2571;
|
|
}
|
|
|
|
/*
|
|
* Initialization functions.
|
|
*/
|
|
static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
|
|
const size_t len)
|
|
{
|
|
unsigned int i;
|
|
int status;
|
|
u32 reg;
|
|
char *ptr = data;
|
|
char *cache;
|
|
int buflen;
|
|
int timeout;
|
|
|
|
/*
|
|
* Wait for stable hardware.
|
|
*/
|
|
for (i = 0; i < 100; i++) {
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
|
|
if (reg)
|
|
break;
|
|
msleep(1);
|
|
}
|
|
|
|
if (!reg) {
|
|
ERROR(rt2x00dev, "Unstable hardware.\n");
|
|
return -EBUSY;
|
|
}
|
|
|
|
/*
|
|
* Write firmware to device.
|
|
* We setup a seperate cache for this action,
|
|
* since we are going to write larger chunks of data
|
|
* then normally used cache size.
|
|
*/
|
|
cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
|
|
if (!cache) {
|
|
ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
|
|
buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
|
|
timeout = REGISTER_TIMEOUT * (buflen / sizeof(u32));
|
|
|
|
memcpy(cache, ptr, buflen);
|
|
|
|
rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
|
|
USB_VENDOR_REQUEST_OUT,
|
|
FIRMWARE_IMAGE_BASE + i, 0x0000,
|
|
cache, buflen, timeout);
|
|
|
|
ptr += buflen;
|
|
}
|
|
|
|
kfree(cache);
|
|
|
|
/*
|
|
* Send firmware request to device to load firmware,
|
|
* we need to specify a long timeout time.
|
|
*/
|
|
status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
|
|
0x0000, USB_MODE_FIRMWARE,
|
|
REGISTER_TIMEOUT_FIRMWARE);
|
|
if (status < 0) {
|
|
ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
|
|
return status;
|
|
}
|
|
|
|
rt73usb_disable_led(rt2x00dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
u32 reg;
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
|
|
rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR1, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
|
|
rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
|
|
|
|
/*
|
|
* CCK TXD BBP registers
|
|
*/
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR2, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
|
|
rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
|
|
|
|
/*
|
|
* OFDM TXD BBP registers
|
|
*/
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR3, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
|
|
rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR7, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
|
|
rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
|
|
rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
|
|
rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR8, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
|
|
rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
|
|
rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
|
|
rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
|
|
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
|
|
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR6, ®);
|
|
rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
|
|
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
|
|
|
|
if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
|
|
return -EBUSY;
|
|
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
|
|
|
|
/*
|
|
* Invalidate all Shared Keys (SEC_CSR0),
|
|
* and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
|
|
*/
|
|
rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
|
|
rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
|
|
rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
|
|
|
|
reg = 0x000023b0;
|
|
if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
|
|
rt2x00_rf(&rt2x00dev->chip, RF2527))
|
|
rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1);
|
|
rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
|
|
|
|
rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
|
|
rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
|
|
rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
|
|
|
|
rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
|
|
rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
|
|
rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
|
|
rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
|
|
rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
|
|
rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
|
|
rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
|
|
rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
|
|
|
|
/*
|
|
* We must clear the error counters.
|
|
* These registers are cleared on read,
|
|
* so we may pass a useless variable to store the value.
|
|
*/
|
|
rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
|
|
rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
|
|
rt73usb_register_read(rt2x00dev, STA_CSR2, ®);
|
|
|
|
/*
|
|
* Reset MAC and BBP registers.
|
|
*/
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
|
|
rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
|
|
rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
|
|
rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
|
|
rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
|
|
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
|
|
rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
unsigned int i;
|
|
u16 eeprom;
|
|
u8 reg_id;
|
|
u8 value;
|
|
|
|
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
rt73usb_bbp_read(rt2x00dev, 0, &value);
|
|
if ((value != 0xff) && (value != 0x00))
|
|
goto continue_csr_init;
|
|
NOTICE(rt2x00dev, "Waiting for BBP register.\n");
|
|
udelay(REGISTER_BUSY_DELAY);
|
|
}
|
|
|
|
ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
|
|
return -EACCES;
|
|
|
|
continue_csr_init:
|
|
rt73usb_bbp_write(rt2x00dev, 3, 0x80);
|
|
rt73usb_bbp_write(rt2x00dev, 15, 0x30);
|
|
rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
|
|
rt73usb_bbp_write(rt2x00dev, 22, 0x38);
|
|
rt73usb_bbp_write(rt2x00dev, 23, 0x06);
|
|
rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
|
|
rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
|
|
rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
|
|
rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
|
|
rt73usb_bbp_write(rt2x00dev, 34, 0x12);
|
|
rt73usb_bbp_write(rt2x00dev, 37, 0x07);
|
|
rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
|
|
rt73usb_bbp_write(rt2x00dev, 41, 0x60);
|
|
rt73usb_bbp_write(rt2x00dev, 53, 0x10);
|
|
rt73usb_bbp_write(rt2x00dev, 54, 0x18);
|
|
rt73usb_bbp_write(rt2x00dev, 60, 0x10);
|
|
rt73usb_bbp_write(rt2x00dev, 61, 0x04);
|
|
rt73usb_bbp_write(rt2x00dev, 62, 0x04);
|
|
rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
|
|
rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
|
|
rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
|
|
rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
|
|
rt73usb_bbp_write(rt2x00dev, 99, 0x00);
|
|
rt73usb_bbp_write(rt2x00dev, 102, 0x16);
|
|
rt73usb_bbp_write(rt2x00dev, 107, 0x04);
|
|
|
|
DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
|
|
for (i = 0; i < EEPROM_BBP_SIZE; i++) {
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
|
|
|
|
if (eeprom != 0xffff && eeprom != 0x0000) {
|
|
reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
|
|
value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
|
|
DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
|
|
reg_id, value);
|
|
rt73usb_bbp_write(rt2x00dev, reg_id, value);
|
|
}
|
|
}
|
|
DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Device state switch handlers.
|
|
*/
|
|
static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
|
|
enum dev_state state)
|
|
{
|
|
u32 reg;
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
|
|
state == STATE_RADIO_RX_OFF);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
|
|
}
|
|
|
|
static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
/*
|
|
* Initialize all registers.
|
|
*/
|
|
if (rt73usb_init_registers(rt2x00dev) ||
|
|
rt73usb_init_bbp(rt2x00dev)) {
|
|
ERROR(rt2x00dev, "Register initialization failed.\n");
|
|
return -EIO;
|
|
}
|
|
|
|
rt2x00usb_enable_radio(rt2x00dev);
|
|
|
|
/*
|
|
* Enable LED
|
|
*/
|
|
rt73usb_enable_led(rt2x00dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
/*
|
|
* Disable LED
|
|
*/
|
|
rt73usb_disable_led(rt2x00dev);
|
|
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
|
|
|
|
/*
|
|
* Disable synchronisation.
|
|
*/
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
|
|
|
|
rt2x00usb_disable_radio(rt2x00dev);
|
|
}
|
|
|
|
static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
|
|
{
|
|
u32 reg;
|
|
unsigned int i;
|
|
char put_to_sleep;
|
|
char current_state;
|
|
|
|
put_to_sleep = (state != STATE_AWAKE);
|
|
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
|
|
rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
|
|
rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
|
|
rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
|
|
|
|
/*
|
|
* Device is not guaranteed to be in the requested state yet.
|
|
* We must wait until the register indicates that the
|
|
* device has entered the correct state.
|
|
*/
|
|
for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
|
|
current_state =
|
|
rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
|
|
if (current_state == !put_to_sleep)
|
|
return 0;
|
|
msleep(10);
|
|
}
|
|
|
|
NOTICE(rt2x00dev, "Device failed to enter state %d, "
|
|
"current device state %d.\n", !put_to_sleep, current_state);
|
|
|
|
return -EBUSY;
|
|
}
|
|
|
|
static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
|
|
enum dev_state state)
|
|
{
|
|
int retval = 0;
|
|
|
|
switch (state) {
|
|
case STATE_RADIO_ON:
|
|
retval = rt73usb_enable_radio(rt2x00dev);
|
|
break;
|
|
case STATE_RADIO_OFF:
|
|
rt73usb_disable_radio(rt2x00dev);
|
|
break;
|
|
case STATE_RADIO_RX_ON:
|
|
case STATE_RADIO_RX_OFF:
|
|
rt73usb_toggle_rx(rt2x00dev, state);
|
|
break;
|
|
case STATE_DEEP_SLEEP:
|
|
case STATE_SLEEP:
|
|
case STATE_STANDBY:
|
|
case STATE_AWAKE:
|
|
retval = rt73usb_set_state(rt2x00dev, state);
|
|
break;
|
|
default:
|
|
retval = -ENOTSUPP;
|
|
break;
|
|
}
|
|
|
|
return retval;
|
|
}
|
|
|
|
/*
|
|
* TX descriptor initialization
|
|
*/
|
|
static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
|
|
__le32 *txd,
|
|
struct txdata_entry_desc *desc,
|
|
struct ieee80211_hdr *ieee80211hdr,
|
|
unsigned int length,
|
|
struct ieee80211_tx_control *control)
|
|
{
|
|
u32 word;
|
|
|
|
/*
|
|
* Start writing the descriptor words.
|
|
*/
|
|
rt2x00_desc_read(txd, 1, &word);
|
|
rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
|
|
rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
|
|
rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
|
|
rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
|
|
rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
|
|
rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
|
|
rt2x00_desc_write(txd, 1, word);
|
|
|
|
rt2x00_desc_read(txd, 2, &word);
|
|
rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
|
|
rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
|
|
rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
|
|
rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
|
|
rt2x00_desc_write(txd, 2, word);
|
|
|
|
rt2x00_desc_read(txd, 5, &word);
|
|
rt2x00_set_field32(&word, TXD_W5_TX_POWER,
|
|
TXPOWER_TO_DEV(control->power_level));
|
|
rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
|
|
rt2x00_desc_write(txd, 5, word);
|
|
|
|
rt2x00_desc_read(txd, 0, &word);
|
|
rt2x00_set_field32(&word, TXD_W0_BURST,
|
|
test_bit(ENTRY_TXD_BURST, &desc->flags));
|
|
rt2x00_set_field32(&word, TXD_W0_VALID, 1);
|
|
rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
|
|
test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
|
|
rt2x00_set_field32(&word, TXD_W0_ACK,
|
|
test_bit(ENTRY_TXD_ACK, &desc->flags));
|
|
rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
|
|
test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
|
|
rt2x00_set_field32(&word, TXD_W0_OFDM,
|
|
test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
|
|
rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
|
|
rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
|
|
!!(control->flags &
|
|
IEEE80211_TXCTL_LONG_RETRY_LIMIT));
|
|
rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
|
|
rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
|
|
rt2x00_set_field32(&word, TXD_W0_BURST2,
|
|
test_bit(ENTRY_TXD_BURST, &desc->flags));
|
|
rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
|
|
rt2x00_desc_write(txd, 0, word);
|
|
}
|
|
|
|
static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
|
|
struct sk_buff *skb)
|
|
{
|
|
int length;
|
|
|
|
/*
|
|
* The length _must_ be a multiple of 4,
|
|
* but it must _not_ be a multiple of the USB packet size.
|
|
*/
|
|
length = roundup(skb->len, 4);
|
|
length += (4 * !(length % rt2x00dev->usb_maxpacket));
|
|
|
|
return length;
|
|
}
|
|
|
|
/*
|
|
* TX data initialization
|
|
*/
|
|
static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
|
|
unsigned int queue)
|
|
{
|
|
u32 reg;
|
|
|
|
if (queue != IEEE80211_TX_QUEUE_BEACON)
|
|
return;
|
|
|
|
/*
|
|
* For Wi-Fi faily generated beacons between participating stations.
|
|
* Set TBTT phase adaptive adjustment step to 8us (default 16us)
|
|
*/
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
|
|
if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
|
|
rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* RX control handlers
|
|
*/
|
|
static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
|
|
{
|
|
u16 eeprom;
|
|
u8 offset;
|
|
u8 lna;
|
|
|
|
lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
|
|
switch (lna) {
|
|
case 3:
|
|
offset = 90;
|
|
break;
|
|
case 2:
|
|
offset = 74;
|
|
break;
|
|
case 1:
|
|
offset = 64;
|
|
break;
|
|
default:
|
|
return 0;
|
|
}
|
|
|
|
if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
|
|
if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
|
|
if (lna == 3 || lna == 2)
|
|
offset += 10;
|
|
} else {
|
|
if (lna == 3)
|
|
offset += 6;
|
|
else if (lna == 2)
|
|
offset += 8;
|
|
}
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
|
|
offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
|
|
} else {
|
|
if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
|
|
offset += 14;
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
|
|
offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
|
|
}
|
|
|
|
return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
|
|
}
|
|
|
|
static void rt73usb_fill_rxdone(struct data_entry *entry,
|
|
struct rxdata_entry_desc *desc)
|
|
{
|
|
__le32 *rxd = (__le32 *)entry->skb->data;
|
|
u32 word0;
|
|
u32 word1;
|
|
|
|
rt2x00_desc_read(rxd, 0, &word0);
|
|
rt2x00_desc_read(rxd, 1, &word1);
|
|
|
|
desc->flags = 0;
|
|
if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
|
|
desc->flags |= RX_FLAG_FAILED_FCS_CRC;
|
|
|
|
/*
|
|
* Obtain the status about this packet.
|
|
*/
|
|
desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
|
|
desc->rssi = rt73usb_agc_to_rssi(entry->ring->rt2x00dev, word1);
|
|
desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
|
|
desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
|
|
|
|
/*
|
|
* Pull the skb to clear the descriptor area.
|
|
*/
|
|
skb_pull(entry->skb, entry->ring->desc_size);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Device probe functions.
|
|
*/
|
|
static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
u16 word;
|
|
u8 *mac;
|
|
s8 value;
|
|
|
|
rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
|
|
|
|
/*
|
|
* Start validation of the data that has been read.
|
|
*/
|
|
mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
|
|
if (!is_valid_ether_addr(mac)) {
|
|
DECLARE_MAC_BUF(macbuf);
|
|
|
|
random_ether_addr(mac);
|
|
EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
|
|
}
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
|
|
if (word == 0xffff) {
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
|
|
ANTENNA_B);
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
|
|
ANTENNA_B);
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
|
|
rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
|
|
EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
|
|
}
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
|
|
if (word == 0xffff) {
|
|
rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
|
|
EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
|
|
}
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
|
|
if (word == 0xffff) {
|
|
rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
|
|
rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
|
|
rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
|
|
rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
|
|
rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
|
|
rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
|
|
rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
|
|
rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
|
|
rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
|
|
LED_MODE_DEFAULT);
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
|
|
EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
|
|
}
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
|
|
if (word == 0xffff) {
|
|
rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
|
|
rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
|
|
EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
|
|
}
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
|
|
if (word == 0xffff) {
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
|
|
EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
|
|
} else {
|
|
value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
|
|
if (value < -10 || value > 10)
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
|
|
value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
|
|
if (value < -10 || value > 10)
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
|
|
}
|
|
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
|
|
if (word == 0xffff) {
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
|
|
EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
|
|
} else {
|
|
value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
|
|
if (value < -10 || value > 10)
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
|
|
value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
|
|
if (value < -10 || value > 10)
|
|
rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
|
|
rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
u32 reg;
|
|
u16 value;
|
|
u16 eeprom;
|
|
|
|
/*
|
|
* Read EEPROM word for configuration.
|
|
*/
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
|
|
|
|
/*
|
|
* Identify RF chipset.
|
|
*/
|
|
value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
|
|
rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
|
|
rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
|
|
|
|
if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
|
|
ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
|
|
!rt2x00_rf(&rt2x00dev->chip, RF2528) &&
|
|
!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
|
|
!rt2x00_rf(&rt2x00dev->chip, RF2527)) {
|
|
ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
/*
|
|
* Identify default antenna configuration.
|
|
*/
|
|
rt2x00dev->default_ant.tx =
|
|
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
|
|
rt2x00dev->default_ant.rx =
|
|
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
|
|
|
|
/*
|
|
* Read the Frame type.
|
|
*/
|
|
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
|
|
__set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
|
|
|
|
/*
|
|
* Read frequency offset.
|
|
*/
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
|
|
rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
|
|
|
|
/*
|
|
* Read external LNA informations.
|
|
*/
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
|
|
|
|
if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
|
|
__set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
|
|
__set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
|
|
}
|
|
|
|
/*
|
|
* Store led settings, for correct led behaviour.
|
|
*/
|
|
rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
|
|
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
|
|
rt2x00dev->led_mode);
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
|
|
rt2x00_get_field16(eeprom,
|
|
EEPROM_LED_POLARITY_GPIO_0));
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
|
|
rt2x00_get_field16(eeprom,
|
|
EEPROM_LED_POLARITY_GPIO_1));
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
|
|
rt2x00_get_field16(eeprom,
|
|
EEPROM_LED_POLARITY_GPIO_2));
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
|
|
rt2x00_get_field16(eeprom,
|
|
EEPROM_LED_POLARITY_GPIO_3));
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
|
|
rt2x00_get_field16(eeprom,
|
|
EEPROM_LED_POLARITY_GPIO_4));
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
|
|
rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
|
|
rt2x00_get_field16(eeprom,
|
|
EEPROM_LED_POLARITY_RDY_G));
|
|
rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
|
|
rt2x00_get_field16(eeprom,
|
|
EEPROM_LED_POLARITY_RDY_A));
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* RF value list for RF2528
|
|
* Supports: 2.4 GHz
|
|
*/
|
|
static const struct rf_channel rf_vals_bg_2528[] = {
|
|
{ 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
|
|
{ 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
|
|
{ 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
|
|
{ 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
|
|
{ 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
|
|
{ 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
|
|
{ 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
|
|
{ 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
|
|
{ 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
|
|
{ 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
|
|
{ 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
|
|
{ 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
|
|
{ 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
|
|
{ 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
|
|
};
|
|
|
|
/*
|
|
* RF value list for RF5226
|
|
* Supports: 2.4 GHz & 5.2 GHz
|
|
*/
|
|
static const struct rf_channel rf_vals_5226[] = {
|
|
{ 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
|
|
{ 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
|
|
{ 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
|
|
{ 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
|
|
{ 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
|
|
{ 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
|
|
{ 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
|
|
{ 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
|
|
{ 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
|
|
{ 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
|
|
{ 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
|
|
{ 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
|
|
{ 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
|
|
{ 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
|
|
|
|
/* 802.11 UNI / HyperLan 2 */
|
|
{ 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
|
|
{ 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
|
|
{ 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
|
|
{ 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
|
|
{ 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
|
|
{ 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
|
|
{ 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
|
|
{ 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
|
|
|
|
/* 802.11 HyperLan 2 */
|
|
{ 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
|
|
{ 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
|
|
{ 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
|
|
{ 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
|
|
{ 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
|
|
{ 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
|
|
{ 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
|
|
{ 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
|
|
{ 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
|
|
{ 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
|
|
|
|
/* 802.11 UNII */
|
|
{ 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
|
|
{ 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
|
|
{ 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
|
|
{ 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
|
|
{ 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
|
|
{ 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
|
|
|
|
/* MMAC(Japan)J52 ch 34,38,42,46 */
|
|
{ 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
|
|
{ 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
|
|
{ 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
|
|
{ 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
|
|
};
|
|
|
|
/*
|
|
* RF value list for RF5225 & RF2527
|
|
* Supports: 2.4 GHz & 5.2 GHz
|
|
*/
|
|
static const struct rf_channel rf_vals_5225_2527[] = {
|
|
{ 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
|
|
{ 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
|
|
{ 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
|
|
{ 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
|
|
{ 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
|
|
{ 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
|
|
{ 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
|
|
{ 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
|
|
{ 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
|
|
{ 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
|
|
{ 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
|
|
{ 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
|
|
{ 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
|
|
{ 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
|
|
|
|
/* 802.11 UNI / HyperLan 2 */
|
|
{ 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
|
|
{ 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
|
|
{ 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
|
|
{ 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
|
|
{ 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
|
|
{ 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
|
|
{ 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
|
|
{ 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
|
|
|
|
/* 802.11 HyperLan 2 */
|
|
{ 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
|
|
{ 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
|
|
{ 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
|
|
{ 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
|
|
{ 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
|
|
{ 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
|
|
{ 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
|
|
{ 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
|
|
{ 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
|
|
{ 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
|
|
|
|
/* 802.11 UNII */
|
|
{ 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
|
|
{ 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
|
|
{ 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
|
|
{ 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
|
|
{ 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
|
|
{ 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
|
|
|
|
/* MMAC(Japan)J52 ch 34,38,42,46 */
|
|
{ 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
|
|
{ 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
|
|
{ 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
|
|
{ 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
|
|
};
|
|
|
|
|
|
static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
struct hw_mode_spec *spec = &rt2x00dev->spec;
|
|
u8 *txpower;
|
|
unsigned int i;
|
|
|
|
/*
|
|
* Initialize all hw fields.
|
|
*/
|
|
rt2x00dev->hw->flags =
|
|
IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
|
|
IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
|
|
rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
|
|
rt2x00dev->hw->max_signal = MAX_SIGNAL;
|
|
rt2x00dev->hw->max_rssi = MAX_RX_SSI;
|
|
rt2x00dev->hw->queues = 5;
|
|
|
|
SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
|
|
SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
|
|
rt2x00_eeprom_addr(rt2x00dev,
|
|
EEPROM_MAC_ADDR_0));
|
|
|
|
/*
|
|
* Convert tx_power array in eeprom.
|
|
*/
|
|
txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
|
|
for (i = 0; i < 14; i++)
|
|
txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
|
|
|
|
/*
|
|
* Initialize hw_mode information.
|
|
*/
|
|
spec->num_modes = 2;
|
|
spec->num_rates = 12;
|
|
spec->tx_power_a = NULL;
|
|
spec->tx_power_bg = txpower;
|
|
spec->tx_power_default = DEFAULT_TXPOWER;
|
|
|
|
if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
|
|
spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
|
|
spec->channels = rf_vals_bg_2528;
|
|
} else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
|
|
spec->num_channels = ARRAY_SIZE(rf_vals_5226);
|
|
spec->channels = rf_vals_5226;
|
|
} else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
|
|
spec->num_channels = 14;
|
|
spec->channels = rf_vals_5225_2527;
|
|
} else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
|
|
spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
|
|
spec->channels = rf_vals_5225_2527;
|
|
}
|
|
|
|
if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
|
|
rt2x00_rf(&rt2x00dev->chip, RF5226)) {
|
|
spec->num_modes = 3;
|
|
|
|
txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
|
|
for (i = 0; i < 14; i++)
|
|
txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
|
|
|
|
spec->tx_power_a = txpower;
|
|
}
|
|
}
|
|
|
|
static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
|
|
{
|
|
int retval;
|
|
|
|
/*
|
|
* Allocate eeprom data.
|
|
*/
|
|
retval = rt73usb_validate_eeprom(rt2x00dev);
|
|
if (retval)
|
|
return retval;
|
|
|
|
retval = rt73usb_init_eeprom(rt2x00dev);
|
|
if (retval)
|
|
return retval;
|
|
|
|
/*
|
|
* Initialize hw specifications.
|
|
*/
|
|
rt73usb_probe_hw_mode(rt2x00dev);
|
|
|
|
/*
|
|
* This device requires firmware
|
|
*/
|
|
__set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
|
|
|
|
/*
|
|
* Set the rssi offset.
|
|
*/
|
|
rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* IEEE80211 stack callback functions.
|
|
*/
|
|
static void rt73usb_configure_filter(struct ieee80211_hw *hw,
|
|
unsigned int changed_flags,
|
|
unsigned int *total_flags,
|
|
int mc_count,
|
|
struct dev_addr_list *mc_list)
|
|
{
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
struct interface *intf = &rt2x00dev->interface;
|
|
u32 reg;
|
|
|
|
/*
|
|
* Mask off any flags we are going to ignore from
|
|
* the total_flags field.
|
|
*/
|
|
*total_flags &=
|
|
FIF_ALLMULTI |
|
|
FIF_FCSFAIL |
|
|
FIF_PLCPFAIL |
|
|
FIF_CONTROL |
|
|
FIF_OTHER_BSS |
|
|
FIF_PROMISC_IN_BSS;
|
|
|
|
/*
|
|
* Apply some rules to the filters:
|
|
* - Some filters imply different filters to be set.
|
|
* - Some things we can't filter out at all.
|
|
* - Some filters are set based on interface type.
|
|
*/
|
|
if (mc_count)
|
|
*total_flags |= FIF_ALLMULTI;
|
|
if (*total_flags & FIF_OTHER_BSS ||
|
|
*total_flags & FIF_PROMISC_IN_BSS)
|
|
*total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
|
|
if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
|
|
*total_flags |= FIF_PROMISC_IN_BSS;
|
|
|
|
/*
|
|
* Check if there is any work left for us.
|
|
*/
|
|
if (intf->filter == *total_flags)
|
|
return;
|
|
intf->filter = *total_flags;
|
|
|
|
/*
|
|
* When in atomic context, reschedule and let rt2x00lib
|
|
* call this function again.
|
|
*/
|
|
if (in_atomic()) {
|
|
queue_work(rt2x00dev->hw->workqueue, &rt2x00dev->filter_work);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Start configuration steps.
|
|
* Note that the version error will always be dropped
|
|
* and broadcast frames will always be accepted since
|
|
* there is no filter for it at this time.
|
|
*/
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
|
|
!(*total_flags & FIF_FCSFAIL));
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
|
|
!(*total_flags & FIF_PLCPFAIL));
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
|
|
!(*total_flags & FIF_CONTROL));
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
|
|
!(*total_flags & FIF_PROMISC_IN_BSS));
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
|
|
!(*total_flags & FIF_PROMISC_IN_BSS));
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
|
|
!(*total_flags & FIF_ALLMULTI));
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
|
|
rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
|
|
}
|
|
|
|
static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
|
|
u32 short_retry, u32 long_retry)
|
|
{
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
u32 reg;
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
|
|
rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
|
|
rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#if 0
|
|
/*
|
|
* Mac80211 demands get_tsf must be atomic.
|
|
* This is not possible for rt73usb since all register access
|
|
* functions require sleeping. Untill mac80211 no longer needs
|
|
* get_tsf to be atomic, this function should be disabled.
|
|
*/
|
|
static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
|
|
{
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
u64 tsf;
|
|
u32 reg;
|
|
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR13, ®);
|
|
tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
|
|
rt73usb_register_read(rt2x00dev, TXRX_CSR12, ®);
|
|
tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
|
|
|
|
return tsf;
|
|
}
|
|
#else
|
|
#define rt73usb_get_tsf NULL
|
|
#endif
|
|
|
|
static void rt73usb_reset_tsf(struct ieee80211_hw *hw)
|
|
{
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR12, 0);
|
|
rt73usb_register_write(rt2x00dev, TXRX_CSR13, 0);
|
|
}
|
|
|
|
static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
|
|
struct ieee80211_tx_control *control)
|
|
{
|
|
struct rt2x00_dev *rt2x00dev = hw->priv;
|
|
int timeout;
|
|
|
|
/*
|
|
* Just in case the ieee80211 doesn't set this,
|
|
* but we need this queue set for the descriptor
|
|
* initialization.
|
|
*/
|
|
control->queue = IEEE80211_TX_QUEUE_BEACON;
|
|
|
|
/*
|
|
* First we create the beacon.
|
|
*/
|
|
skb_push(skb, TXD_DESC_SIZE);
|
|
memset(skb->data, 0, TXD_DESC_SIZE);
|
|
|
|
rt2x00lib_write_tx_desc(rt2x00dev, (__le32 *)skb->data,
|
|
(struct ieee80211_hdr *)(skb->data +
|
|
TXD_DESC_SIZE),
|
|
skb->len - TXD_DESC_SIZE, control);
|
|
|
|
/*
|
|
* Write entire beacon with descriptor to register,
|
|
* and kick the beacon generator.
|
|
*/
|
|
timeout = REGISTER_TIMEOUT * (skb->len / sizeof(u32));
|
|
rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
|
|
USB_VENDOR_REQUEST_OUT,
|
|
HW_BEACON_BASE0, 0x0000,
|
|
skb->data, skb->len, timeout);
|
|
rt73usb_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct ieee80211_ops rt73usb_mac80211_ops = {
|
|
.tx = rt2x00mac_tx,
|
|
.start = rt2x00mac_start,
|
|
.stop = rt2x00mac_stop,
|
|
.add_interface = rt2x00mac_add_interface,
|
|
.remove_interface = rt2x00mac_remove_interface,
|
|
.config = rt2x00mac_config,
|
|
.config_interface = rt2x00mac_config_interface,
|
|
.configure_filter = rt73usb_configure_filter,
|
|
.get_stats = rt2x00mac_get_stats,
|
|
.set_retry_limit = rt73usb_set_retry_limit,
|
|
.erp_ie_changed = rt2x00mac_erp_ie_changed,
|
|
.conf_tx = rt2x00mac_conf_tx,
|
|
.get_tx_stats = rt2x00mac_get_tx_stats,
|
|
.get_tsf = rt73usb_get_tsf,
|
|
.reset_tsf = rt73usb_reset_tsf,
|
|
.beacon_update = rt73usb_beacon_update,
|
|
};
|
|
|
|
static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
|
|
.probe_hw = rt73usb_probe_hw,
|
|
.get_firmware_name = rt73usb_get_firmware_name,
|
|
.load_firmware = rt73usb_load_firmware,
|
|
.initialize = rt2x00usb_initialize,
|
|
.uninitialize = rt2x00usb_uninitialize,
|
|
.set_device_state = rt73usb_set_device_state,
|
|
.link_stats = rt73usb_link_stats,
|
|
.reset_tuner = rt73usb_reset_tuner,
|
|
.link_tuner = rt73usb_link_tuner,
|
|
.write_tx_desc = rt73usb_write_tx_desc,
|
|
.write_tx_data = rt2x00usb_write_tx_data,
|
|
.get_tx_data_len = rt73usb_get_tx_data_len,
|
|
.kick_tx_queue = rt73usb_kick_tx_queue,
|
|
.fill_rxdone = rt73usb_fill_rxdone,
|
|
.config_mac_addr = rt73usb_config_mac_addr,
|
|
.config_bssid = rt73usb_config_bssid,
|
|
.config_type = rt73usb_config_type,
|
|
.config_preamble = rt73usb_config_preamble,
|
|
.config = rt73usb_config,
|
|
};
|
|
|
|
static const struct rt2x00_ops rt73usb_ops = {
|
|
.name = DRV_NAME,
|
|
.rxd_size = RXD_DESC_SIZE,
|
|
.txd_size = TXD_DESC_SIZE,
|
|
.eeprom_size = EEPROM_SIZE,
|
|
.rf_size = RF_SIZE,
|
|
.lib = &rt73usb_rt2x00_ops,
|
|
.hw = &rt73usb_mac80211_ops,
|
|
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
|
|
.debugfs = &rt73usb_rt2x00debug,
|
|
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
|
|
};
|
|
|
|
/*
|
|
* rt73usb module information.
|
|
*/
|
|
static struct usb_device_id rt73usb_device_table[] = {
|
|
/* AboCom */
|
|
{ USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Askey */
|
|
{ USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* ASUS */
|
|
{ USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Belkin */
|
|
{ USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Billionton */
|
|
{ USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Buffalo */
|
|
{ USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* CNet */
|
|
{ USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Conceptronic */
|
|
{ USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* D-Link */
|
|
{ USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Gemtek */
|
|
{ USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Gigabyte */
|
|
{ USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Huawei-3Com */
|
|
{ USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Hercules */
|
|
{ USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Linksys */
|
|
{ USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* MSI */
|
|
{ USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Ralink */
|
|
{ USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Qcom */
|
|
{ USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Senao */
|
|
{ USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Sitecom */
|
|
{ USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Surecom */
|
|
{ USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
/* Planex */
|
|
{ USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
|
|
{ 0, }
|
|
};
|
|
|
|
MODULE_AUTHOR(DRV_PROJECT);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
|
|
MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
|
|
MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
|
|
MODULE_FIRMWARE(FIRMWARE_RT2571);
|
|
MODULE_LICENSE("GPL");
|
|
|
|
static struct usb_driver rt73usb_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = rt73usb_device_table,
|
|
.probe = rt2x00usb_probe,
|
|
.disconnect = rt2x00usb_disconnect,
|
|
.suspend = rt2x00usb_suspend,
|
|
.resume = rt2x00usb_resume,
|
|
};
|
|
|
|
static int __init rt73usb_init(void)
|
|
{
|
|
return usb_register(&rt73usb_driver);
|
|
}
|
|
|
|
static void __exit rt73usb_exit(void)
|
|
{
|
|
usb_deregister(&rt73usb_driver);
|
|
}
|
|
|
|
module_init(rt73usb_init);
|
|
module_exit(rt73usb_exit);
|