15d014d131
The way the hardware and firmware work is that there is one shared RX queue and IRQ for a number of different network interfaces. Due to this, we would like to process received packets for every interface in the same NAPI poll handler, so we need a pseudo-device to schedule polling on. What the driver currently does is that it always schedules polling for the first network interface in the list, and processes packets for every interface in the poll handler for that first interface -- however, this scheme breaks down if the first network interface happens to not be up, since netif_rx_schedule_prep() checks netif_running(). sky2 apparently has the same issue, and Stephen Hemminger suggested a way to work around this: create a variant of netif_rx_schedule_prep() that does not check netif_running(). I implemented this locally and called it netif_rx_schedule_prep_notup(), and it seems to work well, but it's something that probably not everyone would be happy with. The ixp2000 is an ARM CPU with a high-speed network interface in the CPU itself (full duplex 4Gb/s or 10Gb/s depending on the IXP model.) The CPU package also contains 8 or 16 (again depending on the IXP model) 'microengines', which are somewhat primitive but very fast and efficient processor cores which can be used to offload various things from the main CPU. This driver makes the high-speed network interface in the CPU visible and usable as a regular linux network device. Currently, it only supports the Radisys ENP2611 IXP board, but adding support for other board types should be fairly easy. Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
409 lines
8.5 KiB
Ucode
409 lines
8.5 KiB
Ucode
/*
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* RX ucode for the Intel IXP2400 in POS-PHY mode.
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* Copyright (C) 2004, 2005 Lennert Buytenhek
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* Dedicated to Marija Kulikova.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* Assumptions made in this code:
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* - The IXP2400 MSF is configured for POS-PHY mode, in a mode where
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* only one full element list is used. This includes, for example,
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* 1x32 SPHY and 1x32 MPHY32, but not 4x8 SPHY or 1x32 MPHY4. (This
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* is not an exhaustive list.)
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* - The RBUF uses 64-byte mpackets.
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* - RX descriptors reside in SRAM, and have the following format:
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* struct rx_desc
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* {
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* // to uengine
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* u32 buf_phys_addr;
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* u32 buf_length;
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*
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* // from uengine
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* u32 channel;
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* u32 pkt_length;
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* };
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* - Packet data resides in DRAM.
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* - Packet buffer addresses are 8-byte aligned.
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* - Scratch ring 0 is rx_pending.
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* - Scratch ring 1 is rx_done, and has status condition 'full'.
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* - The host triggers rx_done flush and rx_pending refill on seeing INTA.
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* - This code is run on all eight threads of the microengine it runs on.
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*
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* Local memory is used for per-channel RX state.
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*/
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#define RX_THREAD_FREELIST_0 0x0030
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#define RBUF_ELEMENT_DONE 0x0044
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#define CHANNEL_FLAGS *l$index0[0]
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#define CHANNEL_FLAG_RECEIVING 1
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#define PACKET_LENGTH *l$index0[1]
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#define PACKET_CHECKSUM *l$index0[2]
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#define BUFFER_HANDLE *l$index0[3]
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#define BUFFER_START *l$index0[4]
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#define BUFFER_LENGTH *l$index0[5]
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#define CHANNEL_STATE_SIZE 24 // in bytes
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#define CHANNEL_STATE_SHIFT 5 // ceil(log2(state size))
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.sig volatile sig1
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.sig volatile sig2
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.sig volatile sig3
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.sig mpacket_arrived
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.reg add_to_rx_freelist
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.reg read $rsw0, $rsw1
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.xfer_order $rsw0 $rsw1
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.reg zero
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/*
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* Initialise add_to_rx_freelist.
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*/
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.begin
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.reg temp
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.reg temp2
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immed[add_to_rx_freelist, RX_THREAD_FREELIST_0]
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immed_w1[add_to_rx_freelist, (&$rsw0 | (&mpacket_arrived << 12))]
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local_csr_rd[ACTIVE_CTX_STS]
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immed[temp, 0]
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alu[temp2, temp, and, 0x1f]
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alu_shf[add_to_rx_freelist, add_to_rx_freelist, or, temp2, <<20]
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alu[temp2, temp, and, 0x80]
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alu_shf[add_to_rx_freelist, add_to_rx_freelist, or, temp2, <<18]
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.end
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immed[zero, 0]
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/*
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* Skip context 0 initialisation?
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*/
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.begin
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br!=ctx[0, mpacket_receive_loop#]
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.end
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/*
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* Initialise local memory.
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*/
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.begin
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.reg addr
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.reg temp
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immed[temp, 0]
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init_local_mem_loop#:
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alu_shf[addr, --, b, temp, <<CHANNEL_STATE_SHIFT]
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local_csr_wr[ACTIVE_LM_ADDR_0, addr]
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nop
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nop
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nop
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immed[CHANNEL_FLAGS, 0]
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alu[temp, temp, +, 1]
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alu[--, temp, and, 0x20]
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beq[init_local_mem_loop#]
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.end
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/*
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* Initialise signal pipeline.
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*/
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.begin
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local_csr_wr[SAME_ME_SIGNAL, (&sig1 << 3)]
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.set_sig sig1
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local_csr_wr[SAME_ME_SIGNAL, (&sig2 << 3)]
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.set_sig sig2
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local_csr_wr[SAME_ME_SIGNAL, (&sig3 << 3)]
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.set_sig sig3
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.end
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mpacket_receive_loop#:
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/*
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* Synchronise and wait for mpacket.
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*/
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.begin
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ctx_arb[sig1]
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local_csr_wr[SAME_ME_SIGNAL, (0x80 | (&sig1 << 3))]
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msf[fast_wr, --, add_to_rx_freelist, 0]
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.set_sig mpacket_arrived
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ctx_arb[mpacket_arrived]
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.set $rsw0 $rsw1
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.end
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/*
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* We halt if we see {inbparerr,parerr,null,soperror}.
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*/
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.begin
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alu_shf[--, 0x1b, and, $rsw0, >>8]
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bne[abort_rswerr#]
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.end
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/*
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* Point local memory pointer to this channel's state area.
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*/
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.begin
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.reg chanaddr
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alu[chanaddr, $rsw0, and, 0x1f]
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alu_shf[chanaddr, --, b, chanaddr, <<CHANNEL_STATE_SHIFT]
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local_csr_wr[ACTIVE_LM_ADDR_0, chanaddr]
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nop
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nop
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nop
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.end
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/*
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* Check whether we received a SOP mpacket while we were already
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* working on a packet, or a non-SOP mpacket while there was no
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* packet pending. (SOP == RECEIVING -> abort) If everything's
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* okay, update the RECEIVING flag to reflect our new state.
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*/
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.begin
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.reg temp
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.reg eop
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#if CHANNEL_FLAG_RECEIVING != 1
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#error CHANNEL_FLAG_RECEIVING is not 1
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#endif
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alu_shf[temp, 1, and, $rsw0, >>15]
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alu[temp, temp, xor, CHANNEL_FLAGS]
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alu[--, temp, and, CHANNEL_FLAG_RECEIVING]
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beq[abort_proterr#]
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alu_shf[eop, 1, and, $rsw0, >>14]
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alu[CHANNEL_FLAGS, temp, xor, eop]
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.end
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/*
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* Copy the mpacket into the right spot, and in case of EOP,
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* write back the descriptor and pass the packet on.
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*/
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.begin
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.reg buffer_offset
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.reg _packet_length
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.reg _packet_checksum
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.reg _buffer_handle
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.reg _buffer_start
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.reg _buffer_length
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/*
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* Determine buffer_offset, _packet_length and
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* _packet_checksum.
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*/
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.begin
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.reg temp
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alu[--, 1, and, $rsw0, >>15]
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beq[not_sop#]
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immed[PACKET_LENGTH, 0]
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immed[PACKET_CHECKSUM, 0]
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not_sop#:
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alu[buffer_offset, --, b, PACKET_LENGTH]
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alu_shf[temp, 0xff, and, $rsw0, >>16]
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alu[_packet_length, buffer_offset, +, temp]
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alu[PACKET_LENGTH, --, b, _packet_length]
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immed[temp, 0xffff]
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alu[temp, $rsw1, and, temp]
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alu[_packet_checksum, PACKET_CHECKSUM, +, temp]
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alu[PACKET_CHECKSUM, --, b, _packet_checksum]
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.end
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/*
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* Allocate buffer in case of SOP.
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*/
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.begin
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.reg temp
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alu[temp, 1, and, $rsw0, >>15]
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beq[skip_buffer_alloc#]
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.begin
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.sig zzz
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.reg read $stemp $stemp2
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.xfer_order $stemp $stemp2
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rx_nobufs#:
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scratch[get, $stemp, zero, 0, 1], ctx_swap[zzz]
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alu[_buffer_handle, --, b, $stemp]
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beq[rx_nobufs#]
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sram[read, $stemp, _buffer_handle, 0, 2],
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ctx_swap[zzz]
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alu[_buffer_start, --, b, $stemp]
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alu[_buffer_length, --, b, $stemp2]
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.end
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skip_buffer_alloc#:
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.end
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/*
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* Resynchronise.
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*/
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.begin
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ctx_arb[sig2]
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local_csr_wr[SAME_ME_SIGNAL, (0x80 | (&sig2 << 3))]
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.end
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/*
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* Synchronise buffer state.
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*/
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.begin
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.reg temp
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alu[temp, 1, and, $rsw0, >>15]
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beq[copy_from_local_mem#]
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alu[BUFFER_HANDLE, --, b, _buffer_handle]
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alu[BUFFER_START, --, b, _buffer_start]
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alu[BUFFER_LENGTH, --, b, _buffer_length]
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br[sync_state_done#]
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copy_from_local_mem#:
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alu[_buffer_handle, --, b, BUFFER_HANDLE]
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alu[_buffer_start, --, b, BUFFER_START]
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alu[_buffer_length, --, b, BUFFER_LENGTH]
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sync_state_done#:
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.end
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#if 0
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/*
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* Debug buffer state management.
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*/
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.begin
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.reg temp
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alu[temp, 1, and, $rsw0, >>14]
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beq[no_poison#]
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immed[BUFFER_HANDLE, 0xdead]
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immed[BUFFER_START, 0xdead]
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immed[BUFFER_LENGTH, 0xdead]
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no_poison#:
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immed[temp, 0xdead]
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alu[--, _buffer_handle, -, temp]
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beq[state_corrupted#]
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alu[--, _buffer_start, -, temp]
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beq[state_corrupted#]
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alu[--, _buffer_length, -, temp]
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beq[state_corrupted#]
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.end
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#endif
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/*
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* Check buffer length.
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*/
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.begin
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alu[--, _buffer_length, -, _packet_length]
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blo[buffer_overflow#]
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.end
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/*
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* Copy the mpacket and give back the RBUF element.
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*/
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.begin
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.reg element
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.reg xfer_size
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.reg temp
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.sig copy_sig
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alu_shf[element, 0x7f, and, $rsw0, >>24]
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alu_shf[xfer_size, 0xff, and, $rsw0, >>16]
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alu[xfer_size, xfer_size, -, 1]
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alu_shf[xfer_size, 0x10, or, xfer_size, >>3]
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alu_shf[temp, 0x10, or, xfer_size, <<21]
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alu_shf[temp, temp, or, element, <<11]
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alu_shf[--, temp, or, 1, <<18]
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dram[rbuf_rd, --, _buffer_start, buffer_offset, max_8],
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indirect_ref, sig_done[copy_sig]
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ctx_arb[copy_sig]
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alu[temp, RBUF_ELEMENT_DONE, or, element, <<16]
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msf[fast_wr, --, temp, 0]
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.end
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/*
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* If EOP, write back the packet descriptor.
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*/
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.begin
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.reg write $stemp $stemp2
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.xfer_order $stemp $stemp2
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.sig zzz
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alu_shf[--, 1, and, $rsw0, >>14]
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beq[no_writeback#]
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alu[$stemp, $rsw0, and, 0x1f]
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alu[$stemp2, --, b, _packet_length]
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sram[write, $stemp, _buffer_handle, 8, 2], ctx_swap[zzz]
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no_writeback#:
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.end
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/*
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* Resynchronise.
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*/
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.begin
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ctx_arb[sig3]
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local_csr_wr[SAME_ME_SIGNAL, (0x80 | (&sig3 << 3))]
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.end
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/*
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* If EOP, put the buffer back onto the scratch ring.
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*/
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.begin
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.reg write $stemp
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.sig zzz
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br_inp_state[SCR_Ring1_Status, rx_done_ring_overflow#]
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alu_shf[--, 1, and, $rsw0, >>14]
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beq[mpacket_receive_loop#]
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alu[--, 1, and, $rsw0, >>10]
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bne[rxerr#]
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alu[$stemp, --, b, _buffer_handle]
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scratch[put, $stemp, zero, 4, 1], ctx_swap[zzz]
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cap[fast_wr, 0, XSCALE_INT_A]
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br[mpacket_receive_loop#]
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rxerr#:
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alu[$stemp, --, b, _buffer_handle]
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scratch[put, $stemp, zero, 0, 1], ctx_swap[zzz]
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br[mpacket_receive_loop#]
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.end
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.end
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abort_rswerr#:
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halt
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abort_proterr#:
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halt
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state_corrupted#:
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halt
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buffer_overflow#:
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halt
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rx_done_ring_overflow#:
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halt
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