3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef __MDSS_DP_PLL_7NM_H
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#define __MDSS_DP_PLL_7NM_H
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#define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL
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#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL
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#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL
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#define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL
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struct dp_pll_db_7nm {
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struct mdss_pll_resources *pll;
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/* lane and orientation settings */
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u8 lane_cnt;
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u8 orientation;
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/* COM PHY settings */
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u32 hsclk_sel;
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u32 dec_start_mode0;
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u32 div_frac_start1_mode0;
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u32 div_frac_start2_mode0;
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u32 div_frac_start3_mode0;
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u32 integloop_gain0_mode0;
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u32 integloop_gain1_mode0;
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u32 vco_tune_map;
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u32 lock_cmp1_mode0;
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u32 lock_cmp2_mode0;
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u32 lock_cmp_en;
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u32 cmn_config;
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u32 txn_tran_drv_emp_en;
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/* PHY vco divider */
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u32 phy_vco_div;
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};
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int dp_vco_set_rate_7nm(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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unsigned long dp_vco_recalc_rate_7nm(struct clk_hw *hw,
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unsigned long parent_rate);
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long dp_vco_round_rate_7nm(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate);
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int dp_vco_prepare_7nm(struct clk_hw *hw);
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void dp_vco_unprepare_7nm(struct clk_hw *hw);
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int dp_mux_set_parent_7nm(void *context,
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unsigned int reg, unsigned int val);
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int dp_mux_get_parent_7nm(void *context,
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unsigned int reg, unsigned int *val);
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#endif /* __MDSS_DP_PLL_7NM_H */
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