b0f2e2222e
This change adds support for dynamic switching of dsi clocks to avoid RF interference issues. Also with dynamic dsi clock switch feature coming into picture, now populate the supported refresh rate as list instead of providing a range. Modify the logic to enumerate all the modes in dsi driver, taking dynamic bit clocks, resolutions and refresh rates into account. Change-Id: I5b6e62bc935cf2234bdd96fcb3c7537b4e735fff Signed-off-by: Sandeep Panda <spanda@codeaurora.org> Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org> Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
58 lines
1.9 KiB
C
58 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DSI_HW_H_
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#define _DSI_HW_H_
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#include <linux/io.h>
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#define DSI_R32(dsi_hw, off) readl_relaxed((dsi_hw)->base + (off))
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#define DSI_W32(dsi_hw, off, val) \
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do {\
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pr_debug("[DSI_%d][%s] - [0x%08x]\n", \
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(dsi_hw)->index, #off, (uint32_t)(val)); \
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writel_relaxed((val), (dsi_hw)->base + (off)); \
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} while (0)
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#define DSI_MMSS_MISC_R32(dsi_hw, off) \
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readl_relaxed((dsi_hw)->mmss_misc_base + (off))
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#define DSI_MMSS_MISC_W32(dsi_hw, off, val) \
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do {\
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pr_debug("[DSI_%d][%s] - [0x%08x]\n", \
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(dsi_hw)->index, #off, val); \
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writel_relaxed((val), (dsi_hw)->mmss_misc_base + (off)); \
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} while (0)
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#define DSI_MISC_R32(dsi_hw, off) \
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readl_relaxed((dsi_hw)->phy_clamp_base + (off))
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#define DSI_MISC_W32(dsi_hw, off, val) \
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do {\
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pr_debug("[DSI_%d][%s] - [0x%08x]\n", \
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(dsi_hw)->index, #off, val); \
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writel_relaxed((val), (dsi_hw)->phy_clamp_base + (off)); \
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} while (0)
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#define DSI_DISP_CC_R32(dsi_hw, off) \
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readl_relaxed((dsi_hw)->disp_cc_base + (off))
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#define DSI_DISP_CC_W32(dsi_hw, off, val) \
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do {\
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pr_debug("[DSI_%d][%s] - [0x%08x]\n", \
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(dsi_hw)->index, #off, val); \
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writel_relaxed((val), (dsi_hw)->disp_cc_base + (off)); \
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} while (0)
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#define DSI_R64(dsi_hw, off) readq_relaxed((dsi_hw)->base + (off))
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#define DSI_W64(dsi_hw, off, val) writeq_relaxed((val), (dsi_hw)->base + (off))
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#define PLL_CALC_DATA(addr0, addr1, data0, data1) \
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(((data1) << 24) | ((((addr1)/4) & 0xFF) << 16) | \
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((data0) << 8) | (((addr0)/4) & 0xFF))
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#define DSI_DYN_REF_REG_W(base, offset, addr0, addr1, data0, data1) \
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writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \
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(base) + (offset))
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#define DSI_GEN_R32(base, offset) readl_relaxed(base + (offset))
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#define DSI_GEN_W32(base, offset, val) writel_relaxed((val), base + (offset))
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#endif /* _DSI_HW_H_ */
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