c0db2ea4e3
Internal clock path handling for the mxc CPUs. Changed against the original Freescale code (and against clocklib for example): - clock rate is always calculated whenever one ask for the current rate (means struct clk has no more a member called "rate"). So switching the PLL base frequency will propagate immediately to all other clocks that are depending on this frequency. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de>
68 lines
2.4 KiB
C
68 lines
2.4 KiB
C
/*
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301, USA.
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*/
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#ifndef __ASM_ARCH_MXC_CLOCK_H__
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#define __ASM_ARCH_MXC_CLOCK_H__
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#ifndef __ASSEMBLY__
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#include <linux/list.h>
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struct module;
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struct clk {
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struct list_head node;
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struct module *owner;
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const char *name;
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int id;
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/* Source clock this clk depends on */
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struct clk *parent;
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/* Secondary clock to enable/disable with this clock */
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struct clk *secondary;
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/* Reference count of clock enable/disable */
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__s8 usecount;
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/* Register bit position for clock's enable/disable control. */
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u8 enable_shift;
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/* Register address for clock's enable/disable control. */
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u32 enable_reg;
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u32 flags;
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/* get the current clock rate (always a fresh value) */
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unsigned long (*get_rate) (struct clk *);
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/* Function ptr to set the clock to a new rate. The rate must match a
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supported rate returned from round_rate. Leave blank if clock is not
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programmable */
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int (*set_rate) (struct clk *, unsigned long);
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/* Function ptr to round the requested clock rate to the nearest
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supported rate that is less than or equal to the requested rate. */
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unsigned long (*round_rate) (struct clk *, unsigned long);
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/* Function ptr to enable the clock. Leave blank if clock can not
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be gated. */
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int (*enable) (struct clk *);
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/* Function ptr to disable the clock. Leave blank if clock can not
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be gated. */
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void (*disable) (struct clk *);
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/* Function ptr to set the parent clock of the clock. */
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int (*set_parent) (struct clk *, struct clk *);
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};
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int clk_register(struct clk *clk);
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void clk_unregister(struct clk *clk);
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
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