android_kernel_xiaomi_sm8350/arch/sh/kernel/cpu
Paul Mundt cd01204b82 sh: Encode L1/L2 cache shape in auxvt.
This adds in the L1I/L1D/L2 cache shape support to their respective
entries in the ELF auxvt, based on the Alpha implementation. We use
this on the userspace libc side for calculating a tightly packed
SHMLBA amongst other things.

Signed-off-by: Paul Mundt <lethal@linux-sh.org>
2008-01-28 13:18:59 +09:00
..
irq sh: comment tidying for sh64->sh migration. 2008-01-28 13:18:58 +09:00
sh2 sh: SH-2A FPU support. 2008-01-28 13:18:57 +09:00
sh2a sh: SH-2A FPU support. 2008-01-28 13:18:57 +09:00
sh3 sh: Preparation for uncached jumps through PMB. 2008-01-28 13:18:59 +09:00
sh4 sh: Support denormalization on SH-4 FPU. 2008-01-28 13:18:59 +09:00
sh4a sh: Add resource of USBF for SH7722. 2007-10-30 13:05:31 +09:00
sh5 sh: comment tidying for sh64->sh migration. 2008-01-28 13:18:58 +09:00
adc.c
clock.c sh: clkfwk: Support multi-level clock propagation. 2007-09-28 11:51:52 +09:00
init.c sh: Encode L1/L2 cache shape in auxvt. 2008-01-28 13:18:59 +09:00
Makefile sh: Move over the SH-5 entry.S. 2008-01-28 13:18:46 +09:00
ubc.S